[U-Boot] [PATCH v1 0/7] Enable high speed and heavy load for DDR4 for LSCH3

[Yuantian Tang]

Hi Jocke,

we achieved deep sleep mode that did exactly what you asked for.
If waken up from deep sleep, soc will resume from uboot and re-initialized DDR controller with contents untouched.
Please refer to drivers/ddr/fsl/fsl_ddr_gen4.c and look at DEEP_SLEEP related code.

Regards,
Yuantian

> -----Original Message-----
> From: Joakim Tjernlund [mailto:joakim.tjernlund at transmode.se]
> Sent: Thursday, November 05, 2015 4:04 PM
> To: Sun York-R58495 <yorksun at freescale.com>; u-boot at lists.denx.de
> Cc: curt at cumulusnetworks.com; Sharma Bhupesh-B45370
> <bhupesh.sharma at freescale.com>; trini at konsulko.com;
> l.majewski at samsung.com; Tang Yuantian-B29983
> <Yuantian.Tang at freescale.com>; Kushwaha Prabhakar-B32579
> <prabhakar at freescale.com>; Liu Shengzhou-B36685
> <Shengzhou.Liu at freescale.com>; yamada.m at jp.panasonic.com
> Subject: Re: [PATCH v1 0/7] Enable high speed and heavy load for DDR4 for
> LSCH3
> 
> On Wed, 2015-11-04 at 10:03 -0800, York Sun wrote:
> > This patch set revises the DDR driver to support higher speed for DDR4
> > under heavy load (two dual-rank DIMMs) for four-chipselect interleaving.
> > Single quad-rank DIMM is not supported yet.
> 
> Hi York
> 
> Seeing these patches reminds me about something I have been mening to
> ask, Is it possible init the ddr controller/ddr ram (using ECC also) but still
> retain (parts of) memory contents?
> 
> I am looking at keeping data at the end of memory when performing a warm
> start, but still init the controll/ddr ram (without D_INIT set).
> This way one could pick up any changes to DDR timing if needed.
> Before reboot, ddr ram is set to Self Refresh(SR).
> 
>  Jocke