[U-Boot] [PATCH v1 0/7] Enable high speed and heavy load for DDR4 for LSCH3

[Yuantian Tang]

> -----Original Message-----
> From: York Sun [mailto:yorksun at freescale.com]
> Sent: Friday, November 06, 2015 1:42 AM
> To: Joakim Tjernlund <joakim.tjernlund at transmode.se>; Tang Yuantian-
> B29983 <Yuantian.Tang at freescale.com>; u-boot at lists.denx.de
> Cc: Kushwaha Prabhakar-B32579 <prabhakar at freescale.com>; Sharma
> Bhupesh-B45370 <bhupesh.sharma at freescale.com>; trini at konsulko.com;
> Liu Shengzhou-B36685 <Shengzhou.Liu at freescale.com>;
> curt at cumulusnetworks.com; l.majewski at samsung.com;
> yamada.m at jp.panasonic.com
> Subject: Re: [PATCH v1 0/7] Enable high speed and heavy load for DDR4 for
> LSCH3
> 
> 
> 
> On 11/05/2015 01:55 AM, Joakim Tjernlund wrote:
> > On Thu, 2015-11-05 at 08:23 +0000, Yuantian Tang wrote:
> >> Hi Jocke,
> >>
> >> we achieved deep sleep mode that did exactly what you asked for.
> >> If waken up from deep sleep, soc will resume from uboot and
> >> re-initialized DDR controller with contents untouched.
> >> Please refer to drivers/ddr/fsl/fsl_ddr_gen4.c and look at DEEP_SLEEP
> related code.
> >
> > Looking at it now and it looks the same as for ddr3? Some questions though:
> >  289		if (is_warm_boot()) {
> >  289                 /* enter self-refresh */
> >  290                 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
> >  291                 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
> >  292                 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
> >
> > Why do you need to force SR here? The DDR RAM must already be in SR at
> this point?
> > I come from CPU reset state so my DDR controller has HW default values
> > so this does not feel safe.
> 
> This may be redundant. If the code runs to this line, it should come back from
> a deep sleep. The core is in reset state but the DDR controller is not. It should
> be in self-refresh mode. I will leave that to Yuantian to comment.
> 
This is mandatory.  the steps are: re-enter SR mode, enable DDR controller, exit SR mode. We do that to smooth the transition and avoid any glitch caused when controller takes over memory.

Regards,
Yuantian
 
> >
> >  293                 /* do board specific memory setup */
> >  294                 board_mem_sleep_setup();
> >  295
> >  296                 temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) |
> SDRAM_CFG_BI);
> > SDRAM_CFG_BI skips a lot(all?) init of DDR RAM. What if you want to
> > change some DDR RAM timing/config due to a bug? Then you would have
> to force a cold start.
> >
> > Do you use ECC? Seems to be some issues with ECC if you skip D_INIT
> >
> 
> To perform a warm start, the data in DDR is preserved. So you don't need to
> init the data again for ECC. To preserve data, you cannot run D_INIT again,
> which will destroy the data for sure.
> 
> York