[U-Boot] Ethernet PHY Power Down

[Michael Welling]

On Fri, Nov 06, 2015 at 07:22:00PM -0200, Fabio Estevam wrote:
> On Fri, Nov 6, 2015 at 6:22 PM, Michael Welling <mwelling at ieee.org> wrote:
> > Lets try this again with list membership.
> >
> > I have run into an issue with a KSZ9031 Gigabit Ethernet PHY on an IMX6 module.
> >
> > After booting into Linux and rebooting the ethernet fails consistently.
> >
> > With a bit of investigation I found that the power-down bit in the PHY control
> > register is being set on reboot.
> >
> > => dhcp
> > BOOTP broadcast 1
> > BOOTP broadcast 2
> > BOOTP broadcast 3
> > BOOTP broadcast 4
> > BOOTP broadcast 5
> > .
> > .
> > Abort
> > => mii dump 1 0
> > 0.     (1940)                 -- PHY control register --
> >   (8000:0000) 0.15    =     0    reset
> >   (4000:0000) 0.14    =     0    loopback
> >   (2040:0040) 0. 6,13 =   b10    speed selection = 1000 Mbps
> >   (1000:1000) 0.12    =     1    A/N enable
> >   (0800:0800) 0.11    =     1    power-down
> >   (0400:0000) 0.10    =     0    isolate
> >   (0200:0000) 0. 9    =     0    restart A/N
> >   (0100:0100) 0. 8    =     1    duplex = full
> >   (0080:0000) 0. 7    =     0    collision test enable
> >   (003f:0000) 0. 5- 0 =     0    (reserved)
> >
> > When I manually toggle the power down bit it starts to work again.
> >
> > => mii write 1 0 1140
> > => dhcp
> > FEC Waiting for PHY auto negotiation to complete........ done
> > BOOTP broadcast 1
> > DHCP client bound to address 192.168.0.12 (62 ms)
> >
> > I tried performing the above steps in the PHY driver code with little luck.
> >
> > When I toggle the bit in the code the first dhcp always fails but then it
> > works on subsequent attempts.
> >
> > Any ideas?
> > Has anyone else seen this issue with other PHYs?
> 
> Could you try to revert 59370f3fc as suggested here?
> https://www.mail-archive.com/u-boot@lists.denx.de/msg191196.html

So I added the following lines to my board_phy_config function and the problem
seems to be fixed:
.
.
	ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);                                                                                                                                                                                                                   
	if (ctl & BMCR_PDOWN) {                                                                                                                                                                                                                                              
		ctl &= ~BMCR_PDOWN;                                                                                                                                                                                                                                          
		phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl);                                                                                                                                                                                                           
		mdelay(15);                                                                                                                                                                                                                                                  
	}
.
.

Should this be handled somewhere in the PHY driver core?