[U-Boot] [PATCH v7 21/21] sf: Add SPI NOR protection mechanism

[Simon Glass]

Hi Fabio,

On 10 November 2015 at 16:51, Fabio Estevam <festevam at gmail.com> wrote:
>
> Hi Simon,
>
> On Tue, Nov 10, 2015 at 10:09 PM, Simon Glass <sjg at chromium.org> wrote:
>
> > This patch breaks chromebook_link - I think because it adds a new
> > operation which is not supported by all flash chips. Those that are
> > not supported (i.e that don't have the 'flash_is_locked' method)
> > should still work.
>
> What is the symptom you are seeing? Which SPI NOR flash does this board have?

It crashes reading the environment:

U-Boot 2015.10-00544-gcad0499 (Nov 10 2015 - 17:06:00 -0700)

CPU:   Intel(R) Core(TM) i5-3427U CPU @ 1.80GHz
DRAM:  2.7 GiB
SF: Detected W25Q64CV with page size 256 Bytes, erase size 4 KiB, total 8 MiB
*** Warning - bad CRC, using default environment

Video: 1280x1024x16
Model: Google Link
SF: Detected W25Q64CV with page size 256 Bytes, erase size 4 KiB, total 8 MiB
Invalid Opcode (Undefined Opcode)
EIP: 0010:[<00000058>] EFLAGS: 00010283
Original EIP :[<52fbb058>]
EAX: 76d46bf0 EBX: acd46c20 ECX: 00010000 EDX: 533f94e0
ESI: 003e0000 EDI: 00000004 EBP: 00010000 ESP: acd3cf58
 DS: 0018 ES: 0018 FS: 0020 GS: 0018 SS: 0018
CR0: 00000033 CR2: 00000000 CR3: 00000000 CR4: 00000000
DR0: 00000000 DR1: 00000000 DR2: 00000000 DR3: 00000000
DR6: ffff0ff0 DR7: 00000400
Stack:
    0xacd3cf98 : 0x00010000
    0xacd3cf94 : 0xacd3dd00
    0xacd3cf90 : 0x00000028
    0xacd3cf8c : 0xacf75917
    0xacd3cf88 : 0x00000a30
    0xacd3cf84 : 0xacd3cf9c
    0xacd3cf80 : 0x00000008
    0xacd3cf7c : 0x00001000
    0xacd3cf78 : 0xacd44480
    0xacd3cf74 : 0x00000a30
    0xacd3cf70 : 0x00000a30
    0xacd3cf6c : 0xacf67e75
    0xacd3cf68 : 0xacd3cfd8
    0xacd3cf64 : 0xacd444c8
    0xacd3cf60 : 0xacd3d00c
    0xacd3cf5c : 0xacf75c74
--->0xacd3cf58 : 0x00010000
    0xacd3cf54 : 0x00010283
    0xacd3cf50 : 0x00000010
    0xacd3cf4c : 0x00000058
### ERROR ### Please RESET the board ###

The flash is W25Q64CV.

Regards,
Simon