[U-Boot] [PATCH v2 3/3] net: zynq: Disable secondary queues

[Michal Simek]

From: "Edgar E. Iglesias" <edgar.iglesias at xilinx.com>

Zynq has no priority queues.
ZynqMP has one priority queue and this change is required
to get ethernet working.
This patch was not needed on ep108 for uknown reason even
it should be used.
Tested on Zynq and ZynqMP.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias at xilinx.com>
Signed-off-by: Michal Simek <michal.simek at xilinx.com>
---

Changes in v2:
- Fix commit message
- Remove FIXME from the driver
- Add macro for the first free TX descriptor - 0 is used by send, 1
  is used by other patch

 drivers/net/zynq_gem.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index f32862fd0b2e..29073fbd6633 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -131,6 +131,10 @@ struct zynq_gem_regs {
 	u32 reserved6[18];
 #define STAT_SIZE	44
 	u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
+	u32 reserved7[164];
+	u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
+	u32 reserved8[15];
+	u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
 };
 
 /* BD descriptors */
@@ -147,6 +151,9 @@ struct emac_bd {
 /* BD separation space */
 #define BD_SEPRN_SPACE	64
 
+/* Setup the first free TX descriptor */
+#define TX_FREE_DESC	2
+
 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */
 struct zynq_gem_priv {
 	struct emac_bd *tx_bd;
@@ -304,6 +311,8 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
 	struct phy_device *phydev;
 	struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
 	struct zynq_gem_priv *priv = dev->priv;
+	struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
+	struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
 	const u32 supported = SUPPORTED_10baseT_Half |
 			SUPPORTED_10baseT_Full |
 			SUPPORTED_100baseT_Half |
@@ -352,6 +361,23 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
 		/* Setup for Network Control register, MDIO, Rx and Tx enable */
 		setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
 
+		/* Disable the second priority queue */
+		dummy_tx_bd->addr = 0;
+		dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
+				ZYNQ_GEM_TXBUF_LAST_MASK|
+				ZYNQ_GEM_TXBUF_USED_MASK;
+
+		dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK |
+				ZYNQ_GEM_RXBUF_NEW_MASK;
+		dummy_rx_bd->status = 0;
+		flush_dcache_range((ulong)&dummy_tx_bd, (ulong)&dummy_tx_bd +
+				   sizeof(dummy_tx_bd));
+		flush_dcache_range((ulong)&dummy_rx_bd, (ulong)&dummy_rx_bd +
+				   sizeof(dummy_rx_bd));
+
+		writel((u32)dummy_tx_bd, &regs->transmit_q1_ptr);
+		writel((u32)dummy_rx_bd, &regs->receive_q1_ptr);
+
 		priv->init++;
 	}
 
-- 
2.5.0