[U-Boot] [PATCH 22/25] dm: Convert PCI MMC over to use DM PCI API
Simon Glass
sjg at chromium.org
Tue Nov 17 04:54:00 CET 2015
At present pci_mmc_init() does not correctly use the PCI function since the
list it passes is not terminated. The array size passed to pci_mmc_init() is
actually not used correctly. Fix this and adjust the pci_mmc_init() to scan
all available MMC devices.
Adjust this code to use the new driver model PCI API.
This should move over to the new MMC uclass at some point.
Signed-off-by: Simon Glass <sjg at chromium.org>
---
arch/x86/cpu/baytrail/valleyview.c | 4 ++--
arch/x86/cpu/quark/quark.c | 4 ++--
arch/x86/cpu/queensbay/topcliff.c | 4 ++--
drivers/mmc/pci_mmc.c | 15 +++++++--------
include/mmc.h | 6 ++----
5 files changed, 15 insertions(+), 18 deletions(-)
diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c
index a009c14..9790c6e 100644
--- a/arch/x86/cpu/baytrail/valleyview.c
+++ b/arch/x86/cpu/baytrail/valleyview.c
@@ -14,12 +14,12 @@
static struct pci_device_id mmc_supported[] = {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDIO },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDCARD },
+ {},
};
int cpu_mmc_init(bd_t *bis)
{
- return pci_mmc_init("ValleyView SDHCI", mmc_supported,
- ARRAY_SIZE(mmc_supported));
+ return pci_mmc_init("ValleyView SDHCI", mmc_supported);
}
#ifndef CONFIG_EFI_APP
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index f737e19..77ae9b8 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -19,6 +19,7 @@
static struct pci_device_id mmc_supported[] = {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO },
+ {},
};
/*
@@ -340,8 +341,7 @@ int arch_early_init_r(void)
int cpu_mmc_init(bd_t *bis)
{
- return pci_mmc_init("Quark SDHCI", mmc_supported,
- ARRAY_SIZE(mmc_supported));
+ return pci_mmc_init("Quark SDHCI", mmc_supported);
}
void cpu_irq_init(void)
diff --git a/arch/x86/cpu/queensbay/topcliff.c b/arch/x86/cpu/queensbay/topcliff.c
index 9faf1b9..b76dd7d 100644
--- a/arch/x86/cpu/queensbay/topcliff.c
+++ b/arch/x86/cpu/queensbay/topcliff.c
@@ -11,10 +11,10 @@
static struct pci_device_id mmc_supported[] = {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 },
+ {},
};
int cpu_mmc_init(bd_t *bis)
{
- return pci_mmc_init("Topcliff SDHCI", mmc_supported,
- ARRAY_SIZE(mmc_supported));
+ return pci_mmc_init("Topcliff SDHCI", mmc_supported);
}
diff --git a/drivers/mmc/pci_mmc.c b/drivers/mmc/pci_mmc.c
index 37171bf..5fb7151 100644
--- a/drivers/mmc/pci_mmc.c
+++ b/drivers/mmc/pci_mmc.c
@@ -11,26 +11,25 @@
#include <sdhci.h>
#include <asm/pci.h>
-int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported,
- int num_ids)
+int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported)
{
struct sdhci_host *mmc_host;
- pci_dev_t devbusfn;
u32 iobase;
int ret;
int i;
- for (i = 0; i < num_ids; i++) {
- devbusfn = pci_find_devices(mmc_supported, i);
- if (devbusfn == -1)
- return -ENODEV;
+ for (i = 0; ; i++) {
+ struct udevice *dev;
+ ret = pci_find_device_id(mmc_supported, i, &dev);
+ if (ret)
+ return ret;
mmc_host = malloc(sizeof(struct sdhci_host));
if (!mmc_host)
return -ENOMEM;
mmc_host->name = (char *)name;
- pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);
+ dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
mmc_host->ioaddr = (void *)iobase;
mmc_host->quirks = 0;
ret = add_sdhci(mmc_host, 0, 0);
diff --git a/include/mmc.h b/include/mmc.h
index cda9a19..a844cf5 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -484,11 +484,9 @@ struct pci_device_id;
* This finds all the matching PCI IDs and sets them up as MMC devices.
*
* @name: Name to use for devices
- * @mmc_supported: PCI IDs to search for
- * @num_ids: Number of elements in @mmc_supported
+ * @mmc_supported: PCI IDs to search for, terminated by {0, 0}
*/
-int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported,
- int num_ids);
+int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported);
/* Set block count limit because of 16 bit register limit on some hardware*/
#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
--
2.6.0.rc2.230.g3dd15c0
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