[U-Boot] u-boot device model SPI + SPI Flash
Hoefle Marco
Marco.Hoefle at nanotronic.ch
Tue Nov 17 11:17:17 CET 2015
Hello Michal, hello Jagan,
for me the Microblaze SPI port in mainline u-boot does not work with DM.
I used Michal's files and modified the addresses and changed Full Ethernet to Ethernet lite and uart to uartlite to match the hardware here. This was not a big step as both Hardware configurations are very similar.
The changes between v2016.01-rc1 and the changed/added files are attached as patch.
Still the same error:
U-Boot 2016.01--95f642905f8dd7c07ac9f5ed49fe14291ab1fb15---00002-g95f6429-dirty (Nov 17 2015 - 10:57:55 +0100)
DRAM: 256 MiB
Invalid bus 0 (err=-19)
*** Warning - spi_flash_probe() failed, using default environment
In Michal's files the dts file is split into several files. Here is the resulting tree directly from the u-boot console:
=> fdt addr 0x8044fda0
=> fdt print
/ {
#address-cells = <0x00000001>;
#size-cells = <0x00000001>;
compatible = "xlnx,microblaze";
model = "Xilinx-AC701-AXI-full-2015.4";
cpus {
#address-cells = <0x00000001>;
#cpus = <0x00000001>;
#size-cells = <0x00000000>;
cpu at 0 {
bus-handle = <0x00000001>;
clock-frequency = <0x05f5e100>;
clocks = <0x00000002>;
compatible = "xlnx,microblaze-9.5";
d-cache-baseaddr = <0x80000000>;
d-cache-highaddr = <0x8fffffff>;
d-cache-line-size = <0x00000020>;
d-cache-size = <0x00004000>;
device_type = "cpu";
i-cache-baseaddr = <0x80000000>;
i-cache-highaddr = <0x8fffffff>;
i-cache-line-size = <0x00000010>;
i-cache-size = <0x00004000>;
interrupt-handle = <0x00000003>;
model = "microblaze,9.5";
timebase-frequency = <0x05f5e100>;
xlnx,addr-tag-bits = <0x00000010>;
xlnx,allow-dcache-wr = <0x00000001>;
xlnx,allow-icache-wr = <0x00000001>;
xlnx,area-optimized = <0x00000000>;
xlnx,async-interrupt = <0x00000001>;
xlnx,avoid-primitives = <0x00000000>;
xlnx,base-vectors = <0x00000000>;
xlnx,branch-target-cache-size = <0x00000000>;
xlnx,cache-byte-size = <0x00004000>;
xlnx,d-axi = <0x00000001>;
xlnx,d-lmb = <0x00000001>;
xlnx,d-lmb-mon = <0x00000000>;
xlnx,data-size = <0x00000020>;
xlnx,dc-axi-mon = <0x00000000>;
xlnx,dcache-addr-tag = <0x00000010>;
xlnx,dcache-always-used = <0x00000001>;
xlnx,dcache-byte-size = <0x00004000>;
xlnx,dcache-data-width = <0x00000000>;
xlnx,dcache-force-tag-lutram = <0x00000000>;
xlnx,dcache-line-len = <0x00000008>;
xlnx,dcache-use-writeback = <0x00000000>;
xlnx,dcache-victims = <0x00000000>;
xlnx,debug-counter-width = <0x00000020>;
xlnx,debug-enabled = <0x00000001>;
xlnx,debug-event-counters = <0x00000005>;
xlnx,debug-external-trace = <0x00000000>;
xlnx,debug-latency-counters = <0x00000001>;
xlnx,debug-profile-size = <0x00000000>;
xlnx,debug-trace-size = <0x00002000>;
xlnx,div-zero-exception = <0x00000001>;
xlnx,dp-axi-mon = <0x00000000>;
xlnx,dynamic-bus-sizing = <0x00000000>;
xlnx,ecc-use-ce-exception = <0x00000000>;
xlnx,edge-is-positive = <0x00000001>;
xlnx,enable-discrete-ports = <0x00000000>;
xlnx,endianness = <0x00000001>;
xlnx,fault-tolerant = <0x00000000>;
xlnx,fpu-exception = <0x00000000>;
xlnx,freq = <0x05f5e100>;
xlnx,fsl-exception = <0x00000000>;
xlnx,fsl-links = <0x00000000>;
xlnx,i-axi = <0x00000000>;
xlnx,i-lmb = <0x00000001>;
xlnx,i-lmb-mon = <0x00000000>;
xlnx,ic-axi-mon = <0x00000000>;
xlnx,icache-always-used = <0x00000001>;
xlnx,icache-data-width = <0x00000000>;
xlnx,icache-force-tag-lutram = <0x00000000>;
xlnx,icache-line-len = <0x00000004>;
xlnx,icache-streams = <0x00000001>;
xlnx,icache-victims = <0x00000008>;
xlnx,ill-opcode-exception = <0x00000001>;
xlnx,imprecise-exceptions = <0x00000000>;
xlnx,interconnect = <0x00000002>;
xlnx,interrupt-is-edge = <0x00000000>;
xlnx,interrupt-mon = <0x00000000>;
xlnx,ip-axi-mon = <0x00000000>;
xlnx,lockstep-select = <0x00000000>;
xlnx,lockstep-slave = <0x00000000>;
xlnx,mmu-dtlb-size = <0x00000004>;
xlnx,mmu-itlb-size = <0x00000002>;
xlnx,mmu-privileged-instr = <0x00000000>;
xlnx,mmu-tlb-access = <0x00000003>;
xlnx,mmu-zones = <0x00000002>;
xlnx,num-sync-ff-clk = <0x00000002>;
xlnx,num-sync-ff-clk-debug = <0x00000002>;
xlnx,num-sync-ff-clk-irq = <0x00000001>;
xlnx,num-sync-ff-dbg-clk = <0x00000001>;
xlnx,number-of-pc-brk = <0x00000001>;
xlnx,number-of-rd-addr-brk = <0x00000000>;
xlnx,number-of-wr-addr-brk = <0x00000000>;
xlnx,opcode-0x0-illegal = <0x00000001>;
xlnx,optimization = <0x00000000>;
xlnx,pc-width = <0x00000020>;
xlnx,pvr = <0x00000002>;
xlnx,pvr-user1 = <0x00000000>;
xlnx,pvr-user2 = <0x00000000>;
xlnx,reset-msr = <0x00000000>;
xlnx,sco = <0x00000000>;
xlnx,trace = <0x00000000>;
xlnx,unaligned-exceptions = <0x00000001>;
xlnx,use-barrel = <0x00000001>;
xlnx,use-branch-target-cache = <0x00000001>;
xlnx,use-config-reset = <0x00000000>;
xlnx,use-dcache = <0x00000001>;
xlnx,use-div = <0x00000001>;
xlnx,use-ext-brk = <0x00000000>;
xlnx,use-ext-nm-brk = <0x00000000>;
xlnx,use-extended-fsl-instr = <0x00000000>;
xlnx,use-fpu = <0x00000000>;
xlnx,use-hw-mul = <0x00000002>;
xlnx,use-icache = <0x00000001>;
xlnx,use-interrupt = <0x00000002>;
xlnx,use-mmu = <0x00000003>;
xlnx,use-msr-instr = <0x00000001>;
xlnx,use-pcmp-instr = <0x00000001>;
xlnx,use-reorder-instr = <0x00000001>;
xlnx,use-stack-protection = <0x00000000>;
};
};
clocks {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
clk_cpu at 0 {
#clock-cells = <0x00000000>;
clock-frequency = <0x05f5e100>;
clock-output-names = "clk_cpu";
compatible = "fixed-clock";
reg = <0x00000000>;
linux,phandle = <0x00000002>;
phandle = <0x00000002>;
};
clk_bus_0 at 1 {
#clock-cells = <0x00000000>;
clock-frequency = <0x05f5e100>;
clock-output-names = "clk_bus_0";
compatible = "fixed-clock";
reg = <0x00000001>;
};
};
amba_pl {
#address-cells = <0x00000001>;
#size-cells = <0x00000001>;
compatible = "simple-bus";
ranges;
linux,phandle = <0x00000001>;
phandle = <0x00000001>;
interrupt-controller at 41200000 {
#interrupt-cells = <0x00000002>;
compatible = "xlnx,xps-intc-1.00.a";
interrupt-controller;
reg = <0x41200000 0x00010000>;
xlnx,kind-of-intr = <0x00000001>;
xlnx,num-intr-inputs = <0x00000003>;
linux,phandle = <0x00000003>;
phandle = <0x00000003>;
};
serial at 40600000 {
clock-frequency = <0x05f5e100>;
compatible = "xlnx,xps-uartlite-1.00.a";
current-speed = <0x0001c200>;
};
axi_quad_spi at 44a10000 {
compatible = "xlnx,xps-spi-2.00.a";
interrupt-parent = <0x00000003>;
interrupts = <0x00000000 0x00000000>;
reg = <0x44a00000 0x00010000>;
xlnx,num-ss-bits = <0x00000001>;
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
flash at 0 {
compatible = "micron,n25q256a13";
reg = <0x00000000>;
#address-cells = <0x00000001>;
#size-cells = <0x00000001>;
spi-max-frequency = <0x017d7840>;
partition at 0x00000000 {
label = "fpga";
reg = <0x00000000 0x00a00000>;
};
partition at 0x00a00000 {
label = "boot";
reg = <0x00a00000 0x00060000>;
};
partition at 0x00a60000 {
label = "bootenv";
reg = <0x00a60000 0x00040000>;
};
partition at 0x00aa0000 {
label = "kernel";
reg = <0x00aa0000 0x00c00000>;
};
partition at 0x016a0000 {
label = "spare";
reg = <0x016a0000 0x00000000>;
};
};
};
};
aliases {
serial0 = "/amba_pl/serial at 40600000";
spi0 = "/amba_pl/axi_quad_spi at 44a10000";
};
chosen {
bootargs = "console=ttyUL0,115200 earlyprintk";
};
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
};
Any hints how to debug this further?
Marco
________________________________________
Von: Michal Simek <michal.simek at xilinx.com>
Gesendet: Donnerstag, 5. November 2015 16:18
An: Hoefle Marco; Michal Simek; Jagan Teki
Cc: u-boot at lists.denx.de; emanuel stiebler
Betreff: Re: AW: AW: AW: [U-Boot] u-boot device model SPI + SPI Flash
Hi,
On 11/05/2015 03:40 PM, Hoefle Marco wrote:
> Hello Michal,
> I have already adapted microblaze-generic.h accordingly (I think):
> #define CONFIG_DM
> #define CONFIG_DM_SPI 1
> # define CONFIG_DM_SPI_FLASH 1
>
> Only with these settings u-boot xilinx_spi.c will compile.
> Without DM driver wont compile and with DM SPI does not work.
I have sent some files to Marco which are working for me.
Thanks,
Michal
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