[U-Boot] [PATCH 2/2] rockchip: rk3036: enable CONFIG_DEBUG_UART, and use ns16550 uart driver

[Lin Huang]

enable this config so we use common uart function in SPL stage

Signed-off-by: Lin Huang <hl at rock-chips.com>
---
 arch/arm/mach-rockchip/rk3036-board-spl.c | 6 ++----
 configs/evb-rk3036_defconfig              | 5 +++++
 include/configs/rk3036_common.h           | 1 +
 3 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-rockchip/rk3036-board-spl.c b/arch/arm/mach-rockchip/rk3036-board-spl.c
index 3a1491c..449d1df 100644
--- a/arch/arm/mach-rockchip/rk3036-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3036-board-spl.c
@@ -5,20 +5,18 @@
  */
 
 #include <common.h>
+#include <debug_uart.h>
 #include <asm/io.h>
 #include <asm/arch/grf_rk3036.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sdram_rk3036.h>
 #include <asm/arch/timer.h>
-#include <asm/arch/uart.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 #define GRF_BASE	0x20008000
 static struct rk3036_grf * const grf = (void *)GRF_BASE;
 
-#define DEBUG_UART_BASE	0x20068000
-
 extern void back_to_bootrom(void);
 
 void board_init_f(ulong dummy)
@@ -34,7 +32,7 @@ void board_init_f(ulong dummy)
 		     GPIO1C2_MASK << GPIO1C2_SHIFT,
 		     GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT |
 		     GPIO1C2_UART2_SIN << GPIO1C2_SHIFT);
-	rk_uart_init((void *)DEBUG_UART_BASE);
+	debug_uart_init();
 #endif
 	rockchip_timer_init();
 	sdram_init();
diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig
index 2e915ff..b383905 100644
--- a/configs/evb-rk3036_defconfig
+++ b/configs/evb-rk3036_defconfig
@@ -24,3 +24,8 @@ CONFIG_DM_MMC=y
 CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_NS16550=y
+CONFIG_DEBUG_UART_BASE=0x20068000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_SHIFT=2
diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h
index f753e68..a6e0fed 100644
--- a/include/configs/rk3036_common.h
+++ b/include/configs/rk3036_common.h
@@ -24,6 +24,7 @@
 #define CONFIG_SYS_TIMER_BASE		0x200440a0 /* TIMER5 */
 #define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
 
+#define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_MEM32
 
-- 
1.9.1