[U-Boot] [PATCH 3/3] fsl/ddr: updated ddr errata-A008378 for arm and power SoCs

[Shengzhou Liu]

DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0,
T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on
LS102x Rev2.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu at freescale.com>
---
 arch/powerpc/include/asm/config_mpc85xx.h |  2 ++
 drivers/ddr/fsl/fsl_ddr_gen4.c            |  9 ++++++---
 include/fsl_errata.h                      | 31 +++++++++++++++++++++++++++++++
 3 files changed, 39 insertions(+), 3 deletions(-)

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index aabe253..6308c6e 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -797,6 +797,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define MAX_QE_RISC			1
 #define QE_NUM_OF_SNUM			28
 #define CONFIG_SYS_FSL_SFP_VER_3_0
+#define CONFIG_SYS_FSL_ERRATUM_A008378
 
 #elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\
 defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
@@ -844,6 +845,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #define MAX_QE_RISC			1
 #define QE_NUM_OF_SNUM			28
 #define CONFIG_SYS_FSL_SFP_VER_3_0
+#define CONFIG_SYS_FSL_ERRATUM_A008378
 
 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
 #define CONFIG_E6500
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index 4eef047..1ef220b 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -10,6 +10,7 @@
 #include <asm/processor.h>
 #include <fsl_immap.h>
 #include <fsl_ddr.h>
+#include <fsl_errata.h>
 
 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
@@ -175,9 +176,11 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	/* Erratum applies when accumulated ECC is used, or DBI is enabled */
 #define IS_ACC_ECC_EN(v) ((v) & 0x4)
 #define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
-	if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) ||
-	    IS_DBI(regs->ddr_sdram_cfg_3))
-		ddr_setbits32(ddr->debug[28], 0x9 << 20);
+	if (has_erratum_a008378()) {
+		if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) ||
+		    IS_DBI(regs->ddr_sdram_cfg_3))
+			ddr_setbits32(&ddr->debug[28], 0x9 << 20);
+	}
 #endif
 
 	/*
diff --git a/include/fsl_errata.h b/include/fsl_errata.h
index 8f81e4c..283cfcf 100644
--- a/include/fsl_errata.h
+++ b/include/fsl_errata.h
@@ -58,4 +58,35 @@ static inline bool has_erratum_a007186(void)
 }
 #endif
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008378
+static inline bool has_erratum_a008378(void)
+{
+	u32 svr = get_svr();
+	u32 soc = SVR_SOC_VER(svr);
+
+
+	switch (soc) {
+#ifdef CONFIG_LS102XA
+	case SOC_VER_LS1020:
+	case SOC_VER_LS1021:
+	case SOC_VER_LS1022:
+	case SOC_VER_SLS1020:
+		return IS_SVR_REV(svr, 1, 0);
+#endif
+#ifdef CONFIG_PPC
+	case SVR_T1023:
+	case SVR_T1024:
+		return IS_SVR_REV(svr, 1, 0);
+	case SVR_T1020:
+	case SVR_T1022:
+	case SVR_T1040:
+	case SVR_T1042:
+		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
+#endif
+	default:
+		return false;
+	}
+}
+#endif
+
 #endif /*  _FSL_ERRATA_H */
-- 
2.1.0.27.g96db324