[U-Boot] socfpga, spl, status

[Jan Viktorin]

On Fri, 20 Nov 2015 17:27:02 +0100
Marek Vasut <marex at denx.de> wrote:

> On Friday, November 20, 2015 at 05:21:08 PM, Marek Vasut wrote:
> > On Friday, November 20, 2015 at 03:49:46 PM, Jan Viktorin wrote:  
> > > Hello Marek and U-Boot community,  
> > [snip]
> > > So, what is the status of the SPL for SoCFPGA in upstream? Does anybody
> > > test all the claimed socfpga platforms?  
> > 
> > I'm testing mostly MCVEVK and SoCkit and ArriaV SoCDK. Dinh, you wanna look
> > at the CV SoCDK issue ? I might be able to set it up later this weekend,
> > but don't hold your breath, I am pretty overloaded.  
> 
> Update, my SoCdk boots just fine:
> 
> U-Boot SPL 2016.01-rc1-00116-g75dfe33 (Nov 20 2015 - 17:24:50)
> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
> drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
> drivers/ddr/altera/sequencer.c: Calibration complete
> Trying to boot from MMC
> 
> 
> U-Boot 2016.01-rc1-00116-g75dfe33 (Nov 20 2015 - 17:24:50 +0100)
> 
> CPU:   Altera SoCFPGA Platform
> FPGA:  Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
> BOOT:  SD/MMC External Transceiver (1.8V)
>        Watchdog enabled
> I2C:   ready
> DRAM:  1 GiB
> MMC:   SOCFPGA DWMMC: 0
> *** Warning - bad CRC, using default environment
> 
> In:    serial
> Out:   serial
> Err:   serial
> Model: Altera SOCFPGA Cyclone V SoC Development Kit
> Net:   No ethernet found.
> Hit any key to stop autoboot:  0 
> =>  
> 
> Best regards,
> Marek Vasut

Hi, thanks for quick replies.

I tried the SoCDK with 2016-rc1 and the default config
socfpga_cyclone5_defconfig. The previous build has used some
customization of the config (I tried to disable EMAC). I build
by the Buildroot using the uclibc toolchain. Installed as

$ sudo dd if=u-boot-spl-dtb.bin.crc of=/dev/sdc1 bs=64k seek=0
$ sudo dd if=u-boot-dtb.img of=/dev/sdc1 bs=64k seek=4

Freezed again:

U-Boot SPL 2016.01-rc1 (Nov 20 2015 - 17:49:39)
drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
drivers/ddr/altera/sequencer.c: Calibration complete


U-Boot 2016.01-rc1 (Nov 20 2015 - 17:49:39 +0100)

CPU:   Altera SoCFPGA Platform
FPGA:  Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
BOOT:  SD/MMC Internal Transceiver (3.0V)
       Watchdog enabled
I2C:   ready
DRAM:  1 GiB
MMC:   SOCFPGA DWMMC: 0
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Model: Altera SOCFPGA Cyclone V SoC Development Kit
Net:
[...freezed...]

Regards
Jan Viktorin

-- 
   Jan Viktorin                  E-mail: Viktorin at RehiveTech.com
   System Architect              Web:    www.RehiveTech.com
   RehiveTech
   Brno, Czech Republic