[U-Boot] Disabling/Enabling the Data Cache

[Fabio Estevam]

Hi Gary,

On Tue, Nov 24, 2015 at 9:38 AM, Gary Bisson
<gary.bisson at boundarydevices.com> wrote:

>> Does anyone have an update on this issue? I just experienced the same
>> problem with an i.MX6SX:
>> Hit any key to stop autoboot:  0
>> => dcache off
>> => dcache on
>> data abort
>> pc : [<bff4a564>]          lr : [<bff4a5f4>]
>> reloc pc : [<87800564>]    lr : [<878005f4>]
>> sp : bf347d70  ip : 00000000     fp : bf34bb48
>> r10: bffa3c58  r9 : bf347ed8     r8 : 00000002
>> r7 : bf349c28  r6 : 00000000     r5 : 00000000  r4 : 00000000
>> r3 : 00a02000  r2 : 32430000     r1 : bff99a70  r0 : 00000001
>> Flags: nZCv  IRQs off  FIQs off  Mode SVC_32
>> Resetting CPU ...
>>
>> Looking at the reloc pc:
>> 87800550 <v7_outer_cache_enable>:
>> 87800550:       e59f304c        ldr     r3, [pc, #76]   ; 878005a4
>> <v7_outer_cache_enable+0x54>
>> 87800554:       e5932104        ldr     r2, [r3, #260]  ; 0x104
>> 87800558:       e3822501        orr     r2, r2, #4194304        ;
>> 0x400000
>> 8780055c:       e5832104        str     r2, [r3, #260]  ; 0x104
>> 87800560:       e5932100        ldr     r2, [r3, #256]  ; 0x100
>> 87800564:       e3c22001        bic     r2, r2, #1
>>
>> Then looking at arch/arm/cpu/armv7/mx6/soc.c, it looks like the cause
>> is:
>> http://git.denx.de/?p=u-boot.git;a=commit;h=b4ed9f8
>>
>> When commenting out "setbits_le32(&pl310->pl310_aux_ctrl,
>> L310_SHARED_ATT_OVERRIDE_ENABLE)", the problem disappears.
>>
>> Should we unset the bit22 when disabling cache?

Thanks for looking into this.

Catalin,

Do you know if we should unset L310_SHARED_ATT_OVERRIDE_ENABLE bit
when disabling cache?

Any suggestions?

Thanks,

Fabio Estevam