[U-Boot] [PATCH] nios2: convert dma mapping to use dm cpu data

[Thomas Chou]

Convert dma mapping to use dm cpu data.

Signed-off-by: Thomas Chou <thomas at wytron.com.tw>
---
 arch/nios2/include/asm/dma-mapping.h | 21 +++++++++++----------
 1 file changed, 11 insertions(+), 10 deletions(-)

diff --git a/arch/nios2/include/asm/dma-mapping.h b/arch/nios2/include/asm/dma-mapping.h
index 1350e3b..403166b 100644
--- a/arch/nios2/include/asm/dma-mapping.h
+++ b/arch/nios2/include/asm/dma-mapping.h
@@ -1,23 +1,24 @@
 #ifndef __ASM_NIOS2_DMA_MAPPING_H
 #define __ASM_NIOS2_DMA_MAPPING_H
 
-/* dma_alloc_coherent() return cache-line aligned allocation which is mapped
+/*
+ * dma_alloc_coherent() return cache-line aligned allocation which is mapped
  * to uncached io region.
- *
- * IO_REGION_BASE should be defined in board config header file
- *   0x80000000 for nommu, 0xe0000000 for mmu
  */
 
 static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
 {
-	void *addr = malloc(len + CONFIG_SYS_DCACHELINE_SIZE);
+	DECLARE_GLOBAL_DATA_PTR;
+	unsigned long addr =
+		(unsigned long)malloc(len + gd->arch.dcache_line_size);
+
 	if (!addr)
 		return 0;
-	flush_dcache((unsigned long)addr, len + CONFIG_SYS_DCACHELINE_SIZE);
-	*handle = ((unsigned long)addr +
-		   (CONFIG_SYS_DCACHELINE_SIZE - 1)) &
-		~(CONFIG_SYS_DCACHELINE_SIZE - 1) & ~(IO_REGION_BASE);
-	return (void *)(*handle | IO_REGION_BASE);
+	flush_dcache(addr, len + gd->arch.dcache_line_size);
+	*handle = (addr + gd->arch.dcache_line_size - 1) &
+		~(gd->arch.dcache_line_size - 1) & ~gd->arch.io_region_base;
+
+	return (void *)(*handle | gd->arch.io_region_base);
 }
 
 #endif /* __ASM_NIOS2_DMA_MAPPING_H */
-- 
2.1.4