[U-Boot] [PATCH 6/6] x86: Allow disabling IGD on Intel Queensbay

Simon Glass sjg at chromium.org
Fri Oct 9 11:36:43 CEST 2015


Hi Bin,

On 7 October 2015 at 09:24, Bin Meng <bmeng.cn at gmail.com> wrote:
> Hi Simon,
>
> On Sat, Oct 3, 2015 at 10:29 PM, Simon Glass <sjg at chromium.org> wrote:
>> Hi Bin,
>>
>> On 1 October 2015 at 08:36, Bin Meng <bmeng.cn at gmail.com> wrote:
>>> Add a Kconfig option to disable the Integrated Graphics Device (IGD)
>>> so that it does not show in the PCI configuration space as a VGA
>>> disaplay controller. This gives a chance for U-Boot to run PCI/PCIe
>>> based graphics card's VGA BIOS and use that for the graphics console.
>>>
>>> Signed-off-by: Bin Meng <bmeng.cn at gmail.com>
>>>
>>> ---
>>>
>>>  arch/x86/cpu/queensbay/Kconfig            |  8 ++++++++
>>>  arch/x86/cpu/queensbay/tnc.c              | 19 +++++++++++++++++++
>>>  arch/x86/include/asm/arch-queensbay/tnc.h |  5 +++++
>>>  include/configs/crownbay.h                |  1 +
>>>  4 files changed, 33 insertions(+)
>>
>> Acked-by: Simon Glass <sjg at chromium.org>
>>
>> But do we really want configs for such device-specific things? I
>> wonder if device tree would be better. E.g. add 'status = "disabled"'
>> in the PCI node.
>>
>
> I am not sure if I understand you correctly. To me 'status =
> "disabled"' is a generic device binding, and when it comes to PCI
> device, how do we define a device is in a 'disabled' state? Is it we
> program the COMMAND register to disable bus master, mem and I/O
> access? Or we program a chipset-specific register (Intel chipset
> normally has such) to make it invisible from PCI configuration space
> completely? And as you said, this is really chipset-specific thing, so
> I chose to do via a platform-specific configuration macro, instead of
> doing such work under a generic bindings ..

Yes we don't have a good way to notice that a driver is disabled - it
will never be bound in that case.

If there were a driver for the SoC, then perhaps we could add config
options to that node. Then the chipset-specific SoC driver could do
the required init.

Regards,
Simon


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