[U-Boot] [PATCH v2] nios2: set default cache configuration in start.S

Thomas Chou thomas at wytron.com.tw
Fri Oct 9 14:11:48 CEST 2015


Set default icache and dcache configuration for start.S.

We want to remove the CONFIG_SYS_{I,D}CACHE_SIZE...
configuration macros. As we are just barely starting from
reset, there is no luxury of device tree.

We will set some maximum cache configuration so that it will
work for most configurations. This is used only in this
start.S. The speed penalty is only once here.

After start up, during board initialization, cpu information
will be extracted from device tree. Then cache flush operations
will have correct cache configurations.

Signed-off-by: Thomas Chou <thomas at wytron.com.tw>
---
v2
  change commit message.

 arch/nios2/cpu/start.S | 22 +++++++++++++++-------
 1 file changed, 15 insertions(+), 7 deletions(-)

diff --git a/arch/nios2/cpu/start.S b/arch/nios2/cpu/start.S
index 17cab6a..8758e7e 100644
--- a/arch/nios2/cpu/start.S
+++ b/arch/nios2/cpu/start.S
@@ -9,6 +9,15 @@
 #include <config.h>
 #include <version.h>
 
+/*
+ * icache and dcache configuration used only for start.S.
+ * the values are chosen so that it will work for all configuration.
+ */
+#define ICACHE_LINE_SIZE	32 /* fixed 32 */
+#define ICACHE_SIZE_MAX		0x10000 /* 64k max */
+#define DCACHE_LINE_SIZE_MIN	4 /* 4, 16, 32 */
+#define DCACHE_SIZE_MAX		0x10000 /* 64k max */
+
 	/* RESTART */
 	.text
 	.global _start, _except_start, _except_end
@@ -22,9 +31,9 @@ _start:
 	 * just be invalidating the cache a second time. If cache
 	 * is not implemented initi behaves as nop.
 	 */
-	ori	r4, r0, %lo(CONFIG_SYS_ICACHELINE_SIZE)
-	movhi	r5, %hi(CONFIG_SYS_ICACHE_SIZE)
-	ori	r5, r5, %lo(CONFIG_SYS_ICACHE_SIZE)
+	ori	r4, r0, %lo(ICACHE_LINE_SIZE)
+	movhi	r5, %hi(ICACHE_SIZE_MAX)
+	ori	r5, r5, %lo(ICACHE_SIZE_MAX)
 0:	initi	r5
 	sub	r5, r5, r4
 	bgt	r5, r0, 0b
@@ -51,10 +60,9 @@ _except_end:
 	 * DCACHE INIT -- if dcache not implemented, initd behaves as
 	 * nop.
 	 */
-	movhi	r4, %hi(CONFIG_SYS_DCACHELINE_SIZE)
-	ori	r4, r4, %lo(CONFIG_SYS_DCACHELINE_SIZE)
-	movhi	r5, %hi(CONFIG_SYS_DCACHE_SIZE)
-	ori	r5, r5, %lo(CONFIG_SYS_DCACHE_SIZE)
+	ori	r4, r0, %lo(DCACHE_LINE_SIZE_MIN)
+	movhi	r5, %hi(DCACHE_SIZE_MAX)
+	ori	r5, r5, %lo(DCACHE_SIZE_MAX)
 	mov	r6, r0
 1:	initd	0(r6)
 	add	r6, r6, r4
-- 
2.1.4



More information about the U-Boot mailing list