[U-Boot] [PATCH] nios2: convert cache flush to use dm cpu data

[Marek Vasut]

On Saturday, October 10, 2015 at 08:32:09 AM, Thomas Chou wrote:
> Hi Marek,

Hi,

> On 10/10/2015 01:55 PM, Thomas Chou wrote:
> > Hi Marek,
> > 
> > On 10/09/2015 10:42 PM, Marek Vasut wrote:
> >>> In nios2, we don't skip the flushing when the inputs are not aligned
> >>> like that of arm926ejs. We always flush all cache lines in the range,
> >>> even if a single byte to flush is in request. So the inputs are rounded
> >>> to get the lower and upper cache lines range inside the cache flush
> >>> functions. The caller need not be aware of the detail.
> >> 
> >> This is incorrect and all the places which produce these unaligned cache
> >> operations must be fixed.
> > 
> > I take a look into the cache flush operations in every arch of u-boot.
> > It turns out that the arm926ejs is the only platform that does such
> > cache line range check and skip. All other ARM and all other arch don't.
> > And the cache flush in Linux don't.
> 
> +arm11, which is based on the same code.
> 
> I see your patch on this range check. I would prefer that the details of
> cache line configuration be kept inside the cache flush operators, and
> need not be exposed to drivers.

Then you'd also need means to allocate variables to aligned memory location
to prevent invalid cache flush. (Linux does this with it's DMA API). We are
much simpler and thus this abstraction is still not available. I wonder if
the overhead of DMA API would be high or not for U-Boot.

> As drivers might be used by different
> arch with different cache implementation, L1,L2..etc. It is not good for
> drivers to adjust the flush range before passing to cache flush operators.

It is even worse if the cache flush operators permit incorrect cache flushes
or invalidations. Like I mentioned before, this can lead to hard to debug
problems when using DMA (at least on ARM).

Best regards,
Marek Vasut