[U-Boot] [PATCH 00/13] x86: Provide a common MRC cache library and enable it for FSP

[Bin Meng]

This series moves existing MRC cache codes in the ivybridge cpu
diretory to a common place and makes some changes so that every
x86 board benefits from it. It also updates FSP support codes
to pass MRC cache data to fsp_init() to speed up boot time.

Currently tested on Intel Bayley Bay board. Minnow Max board should
work as it uses the same FSP that Bayley Bay uses. For Chromebook
I cannot test that, but I see Simon added a TODO in the codes below:

	/*
	 * TODO(sjg at chromium.org): Skip this for now as it causes boot
 	 * problems
 	 */
 	if (0) {
		pei_data->mrc_input = mrc_cache->data;
		pei_data->mrc_input_len = mrc_cache->data_size;
	}

I have no idea what breaks the MRC cache on the Chromebook board.
Simon, you may retest this on top of this series to see if things
go better.


Bin Meng (13):
  x86: Add ENABLE_MRC_CACHE Kconfig option
  x86: Move mrccache.[c|h] to a common place
  x86: Do sanity test on the cache record in mrccache_update()
  x86: Add various minor tidy-ups in mrccache codes
  x86: Add more common routines to manipulate mrc cache
  x86: ivybridge: Use APIs provided in the mrccache lib
  x86: Use struct mrc_region to describe a mrc region
  x86: fsp: Pass mrc cache to fsp_init() and save it to gd after
    fsp_init()
  x86: baytrail: Save mrc cache to spi flash
  x86: Enable mrc cache for bayleybay and minnowmax
  x86: baytrail: Issue full system reset in reset_cpu()
  x86: Remove unused rw-mrc-cache properties in the link and panther dts
    files
  x86: ivybridge: Correct two typos for MRC

 arch/x86/Kconfig                               |   8 ++
 arch/x86/cpu/baytrail/valleyview.c             |  25 +++++
 arch/x86/cpu/ivybridge/Makefile                |   1 -
 arch/x86/cpu/ivybridge/sdram.c                 | 120 ++---------------------
 arch/x86/dts/bayleybay.dts                     |   6 ++
 arch/x86/dts/chromebook_link.dts               |   2 -
 arch/x86/dts/chromebox_panther.dts             |   3 -
 arch/x86/dts/minnowmax.dts                     |   6 ++
 arch/x86/include/asm/arch-ivybridge/mrccache.h |  51 ----------
 arch/x86/include/asm/mrccache.h                | 107 +++++++++++++++++++++
 arch/x86/lib/Makefile                          |   1 +
 arch/x86/lib/fsp/fsp_common.c                  |  30 +++++-
 arch/x86/lib/fsp/fsp_dram.c                    |   6 ++
 arch/x86/{cpu/ivybridge => lib}/mrccache.c     | 128 +++++++++++++++++++++----
 configs/bayleybay_defconfig                    |   1 +
 configs/chromebook_link_defconfig              |   1 +
 configs/chromebox_panther_defconfig            |   1 +
 configs/minnowmax_defconfig                    |   1 +
 doc/README.x86                                 |   1 +
 19 files changed, 313 insertions(+), 186 deletions(-)
 delete mode 100644 arch/x86/include/asm/arch-ivybridge/mrccache.h
 create mode 100644 arch/x86/include/asm/mrccache.h
 rename arch/x86/{cpu/ivybridge => lib}/mrccache.c (51%)

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1.8.2.1