[U-Boot] [Patch V5 11/17] armv8/fsl_lsch3: Change arch to fsl-layerscape
Gong Q.Y.
Qianyu.Gong at freescale.com
Fri Oct 16 10:44:43 CEST 2015
> -----Original Message-----
> From: Prabhakar [mailto:prabhakar at freescale.com]
> Sent: Friday, October 16, 2015 2:20 PM
> To: Gong Qianyu-B52263; u-boot at lists.denx.de
> Cc: Hu Mingkai-B21284; Sun York-R58495; Hou Zhiqiang-B48286; Xie Shaohui-
> B21989; Song Wenbin-B53747; Wood Scott-B07421; Wang Huan-B18965
> Subject: Re: [Patch V5 11/17] armv8/fsl_lsch3: Change arch to fsl-
> layerscape
>
>
>
> On 10/15/2015 6:32 PM, Gong Qianyu wrote:
> > From: Mingkai Hu <Mingkai.Hu at freescale.com>
> >
> > There are two LS series processors are built on ARMv8 Layersacpe
> > architecture currently, LS2085A and LS1043A. They are based on
> > ARMv8 core although use different chassis, so create fsl-layerscape
> > to refactor the common code for the LS series processors which also
> > paves the way for adding LS1043A platform.
> >
> > Signed-off-by: Mingkai Hu <Mingkai.Hu at freescale.com>
> > Signed-off-by: Gong Qianyu <Qianyu.Gong at freescale.com>
> > ---
> > V5:
> > - Move LS2085A ddr macros out of soc #ifdef.
> > - Move macros and structs from cpu.c to cpu.h.
> > - Wrap le32 and be32 functions for ccsr gur and scfg. Defined in
> soc.h
> > - Modify fsl-layerscape/Makefile.
> > V4:
> > - New patch.
> >
> > arch/arm/cpu/armv8/Makefile | 2 +-
> > arch/arm/cpu/armv8/fsl-layerscape/Makefile | 21 ++
> > .../README => fsl-layerscape/README.lsch3} | 0
> > .../cpu/armv8/{fsl-lsch3 => fsl-layerscape}/cpu.c | 249 ++++++------
> ---------
> > .../cpu/armv8/{fsl-lsch3 => fsl-layerscape}/cpu.h | 2 +-
> > .../cpu/armv8/{fsl-lsch3 => fsl-layerscape}/fdt.c | 17 +-
> > .../fsl_lsch3_serdes.c | 8 +-
> > .../speed.c => fsl-layerscape/fsl_lsch3_speed.c} | 12 +-
> > .../armv8/{fsl-lsch3 => fsl-layerscape}/lowlevel.S | 14 +-
> > .../{fsl-lsch3 => fsl-layerscape}/ls2085a_serdes.c | 3 +-
> > .../cpu/armv8/{fsl-lsch3 => fsl-layerscape}/mp.c | 15 +-
> > .../cpu/armv8/{fsl-lsch3 => fsl-layerscape}/soc.c | 35 +--
> > arch/arm/cpu/armv8/fsl-layerscape/spl.c | 76 +++++++
> > arch/arm/cpu/armv8/fsl-lsch3/Makefile | 13 --
> > arch/arm/cpu/armv8/fsl-lsch3/speed.h | 7 -
> > .../clock.h | 8 +-
> > arch/arm/include/asm/arch-fsl-layerscape/config.h | 59 +++++
> > arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 165
> ++++++++++++++
> > .../{arch-fsl-lsch3 => arch-fsl-layerscape}/fdt.h | 4 +
> > .../fsl_serdes.h | 11 +-
> > .../immap_lsch3.h | 119 ++++++++--
> > .../arm/include/asm/arch-fsl-layerscape/imx-regs.h | 55 +++++
> > .../ls2085a_stream_id.h | 0
> > arch/arm/include/asm/arch-fsl-layerscape/mmu.h | 10 +
> > .../asm/arch-fsl-layerscape}/mp.h | 10 +-
> > .../{arch-fsl-lsch3 => arch-fsl-layerscape}/soc.h | 21 +-
> > arch/arm/include/asm/arch-fsl-layerscape/speed.h | 10 +
> > arch/arm/include/asm/arch-fsl-lsch3/config.h | 185 ------------
> ---
> > arch/arm/include/asm/arch-fsl-lsch3/gpio.h | 9 -
> > arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h | 13 --
> > arch/arm/include/asm/config.h | 7 +-
> > arch/arm/include/asm/global_data.h | 2 +-
> > board/freescale/ls2085aqds/Kconfig | 2 +-
> > board/freescale/ls2085aqds/eth.c | 1 -
> > board/freescale/ls2085aqds/ls2085aqds.c | 2 +-
> > board/freescale/ls2085ardb/Kconfig | 2 +-
> > board/freescale/ls2085ardb/eth_ls2085rdb.c | 1 -
> > board/freescale/ls2085ardb/ls2085ardb.c | 2 +-
> > drivers/i2c/mxc_i2c.c | 4 +-
> > drivers/misc/fsl_debug_server.c | 1 -
> > drivers/net/ldpaa_eth/ls2085a.c | 2 -
> > drivers/pci/pcie_layerscape.c | 4 +-
> > include/common.h | 3 +
> > include/configs/ls2085a_common.h | 47 +++-
> > 44 files changed, 712 insertions(+), 521 deletions(-)
> >
> > diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
> b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
> > similarity index 94%
> > rename from arch/arm/cpu/armv8/fsl-lsch3/fdt.c
> > rename to arch/arm/cpu/armv8/fsl-layerscape/fdt.c
> > index 567c419..aa88d34 100644
> > --- a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
> > @@ -1,5 +1,5 @@
> > /*
> > - * Copyright 2014 Freescale Semiconductor, Inc.
> > + * Copyright 2014-2015 Freescale Semiconductor, Inc.
> > *
> > * SPDX-License-Identifier: GPL-2.0+
> > */
> > @@ -7,11 +7,16 @@
> > #include <common.h>
> > #include <libfdt.h>
> > #include <fdt_support.h>
> > -#include <asm/arch-fsl-lsch3/fdt.h>
> > +#include <phy.h>
> > +#ifdef CONFIG_FSL_LSCH3
> > +#include <asm/arch/fdt.h>
> > +#endif
> > #ifdef CONFIG_FSL_ESDHC
> > #include <fsl_esdhc.h>
> > #endif
> > -#include "mp.h"
> > +#ifdef CONFIG_MP
> > +#include <asm/arch/mp.h>
> > +#endif
> >
> > #ifdef CONFIG_MP
> > void ft_fixup_cpu(void *blob)
> > @@ -150,6 +155,7 @@ void append_mmu_masters(void *blob, const char
> *smmu_path,
> > * for all DPAA2 devices.
> > *
> > */
> > +#ifdef CONFIG_FSL_LSCH3
> > static void fdt_fixup_smmu(void *blob)
> > {
> > int nodeoffset;
> > @@ -165,6 +171,7 @@ static void fdt_fixup_smmu(void *blob)
> > fdt_fixup_smmu_pcie(blob);
> > #endif
> > }
> > +#endif
> >
>
> SMMU fixup should be independent of chassis-generation
>
> > void ft_cpu_setup(void *blob, bd_t *bd)
> > {
> > @@ -181,9 +188,11 @@ void ft_cpu_setup(void *blob, bd_t *bd)
> > ft_pci_setup(blob, bd);
> > #endif
> >
> > -#if defined(CONFIG_FSL_ESDHC)
> > +#ifdef CONFIG_FSL_ESDHC
> > fdt_fixup_esdhc(blob, bd);
> > #endif
> >
> > +#ifdef CONFIG_FSL_LSCH3
> > fdt_fixup_smmu(blob);
> > +#endif
> SMMU fixup should be independent of chassis-generation
>
> > }
I agree. But currently LS1043A hasn't implemented the SMMU and pcie fixup.
We will remove the lsch3 limitation once we add the fixup in the near future.
> > diff --git a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
> b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
> > similarity index 97%
> > rename from arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
> > rename to arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
> > index 6b19d36..2158a8b 100644
> > --- a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
> > @@ -1,5 +1,5 @@
> > /*
> > - * (C) Copyright 2014 Freescale Semiconductor
> > + * (C) Copyright 2014-2015 Freescale Semiconductor
> > *
> > * SPDX-License-Identifier: GPL-2.0+
> > *
> > @@ -10,11 +10,14 @@
> > #include <linux/linkage.h>
> > #include <asm/gic.h>
> > #include <asm/macro.h>
> > -#include "mp.h"
> > +#ifdef CONFIG_MP
> > +#include <asm/arch/mp.h>
> > +#endif
> >
> > ENTRY(lowlevel_init)
> > mov x29, lr /* Save LR */
> >
> > +#ifdef CONFIG_FSL_LSCH3
> > /* Add fully-coherent masters to DVM domain */
> > ldr x0, =CCI_MN_BASE
> > ldr x1, =CCI_MN_RNF_NODEID_LIST
> > @@ -81,6 +84,7 @@ ENTRY(lowlevel_init)
> > ldr x0, =CCI_S2_QOS_CONTROL_BASE(20)
> > ldr x1, =0x00FF000C
> > bl ccn504_set_qos
> > +#endif
> >
> > /* Set the SMMU page size in the sACR register */
> > ldr x1, =SMMU_BASE
> > @@ -106,10 +110,12 @@ ENTRY(lowlevel_init)
> >
> > branch_if_master x0, x1, 2f
> >
> > +#ifdef CONFIG_MP
>
> it should be CONFIG_MP && CONFIG_ARMV8_MULTIENTRY
>
What's the difference between them?
Most of the current code uses CONFIG_MP alone instead of adding CONFIG_ARMV8_MULTIENTRY.
> > ldr x0, =secondary_boot_func
> > blr x0
> > -2:
> > +#endif
> >
> > +2:
> > #ifdef CONFIG_FSL_TZPC_BP147
> > /* Set Non Secure access for all devices protected via TZPC */
> > ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
> > @@ -245,6 +251,7 @@ ENTRY(__asm_flush_l3_cache)
> > ret
> > ENDPROC(__asm_flush_l3_cache)
> >
> > +#ifdef CONFIG_MP
> > /* Keep literals not used by the secondary boot code outside it */
> > .ltorg
> >
> > @@ -353,3 +360,4 @@ __real_cntfrq:
> > /* Secondary Boot Code ends here */
> > __secondary_boot_code_size:
> > .quad .-secondary_boot_code
> > +#endif
> > diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.c
> b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
> > similarity index 93%
> > rename from arch/arm/cpu/armv8/fsl-lsch3/mp.c
> > rename to arch/arm/cpu/armv8/fsl-layerscape/mp.c
> > index da7853a..04eaad6 100644
> > --- a/arch/arm/cpu/armv8/fsl-lsch3/mp.c
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
> > @@ -1,5 +1,5 @@
> > /*
> > - * Copyright 2014 Freescale Semiconductor, Inc.
> > + * Copyright 2014-2015 Freescale Semiconductor, Inc.
> > *
> > * SPDX-License-Identifier: GPL-2.0+
> > */
> > @@ -7,9 +7,8 @@
> > #include <common.h>
> > #include <asm/io.h>
> > #include <asm/system.h>
> > -#include <asm/io.h>
> > -#include <asm/arch-fsl-lsch3/immap_lsch3.h>
> > -#include "mp.h"
> > +#include <asm/arch/mp.h>
> > +#include <asm/arch/soc.h>
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > @@ -23,6 +22,7 @@ phys_addr_t determine_mp_bootpg(void)
> > return (phys_addr_t)&secondary_boot_code;
> > }
> >
> > +#ifdef CONFIG_LS2085A
>
> Please use CONFIG_FSL_LSCH3
Ok.
> > diff --git a/arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h
> b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
> > similarity index 88%
> > rename from arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h
> > rename to arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
> > index 2810f3f..730c2b2 100644
> > --- a/arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h
> > +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
> > @@ -4,13 +4,12 @@
> > * SPDX-License-Identifier: GPL-2.0+
> > */
> >
> > -#ifndef __FSL_SERDES_H
> > -#define __FSL_SERDES_H
> > +#ifndef __FSL_SERDES_H__
> > +#define __FSL_SERDES_H__
> >
> > #include <config.h>
> >
> > -#define SRDS_MAX_LANES 8
> > -
> > +#if defined(CONFIG_LS2085A)
>
> Please avoid putting this code in any #ifdef
>
The LS1043A and LS2085A use different enum srds_prtcl and enum srds.
So we use SOC macros to wrap them up temporarily. This will be revised in the future.
Now we are trying to catch up with the upstream merge window next week.
> > enum srds_prtcl {
> > NONE = 0,
> > PCIE1,
> > @@ -56,12 +55,12 @@ enum srds {
> > FSL_SRDS_1 = 0,
> > FSL_SRDS_2 = 1,
> > };
> > +#endif
> >
> > int is_serdes_configured(enum srds_prtcl device);
> > void fsl_serdes_init(void);
> > -
> > int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
> > enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
> > int is_serdes_prtcl_valid(int serdes, u32 prtcl);
> >
> > -#endif /* __FSL_SERDES_H */
> > +#endif /* __FSL_SERDES_H__ */
> > diff --git a/include/common.h b/include/common.h
> > index ecb1f06..142936b 100644
> > --- a/include/common.h
> > +++ b/include/common.h
> > @@ -76,6 +76,9 @@ typedef volatile unsigned char vu_char;
> > #ifdef CONFIG_SOC_DA8XX
> > #include <asm/arch/hardware.h>
> > #endif
> > +#ifdef CONFIG_FSL_LSCH3
> > +#include <asm/arch/immap_lsch3.h>
> > +#endif
> >
> > #include <part.h>
> > #include <flash.h>
> > diff --git a/include/configs/ls2085a_common.h
> b/include/configs/ls2085a_common.h
> > index 55b909c..5674227 100644
> > --- a/include/configs/ls2085a_common.h
> > +++ b/include/configs/ls2085a_common.h
> > @@ -10,21 +10,63 @@
> > #define CONFIG_SYS_GENERIC_BOARD
> >
> > #define CONFIG_REMAKE_ELF
> > +#define CONFIG_FSL_LAYERSCAPE
> > #define CONFIG_FSL_LSCH3
> > #define CONFIG_LS2085A
> > +#define CONFIG_MP
> > #define CONFIG_GICV3
> > #define CONFIG_FSL_TZPC_BP147
> >
> > +/* Generic Interrupt Controller Definitions */
> > +#define GICD_BASE 0x06000000
> > +#define GICR_BASE 0x06100000
> > +
> > +/* SMMU Defintions */
> > +#define SMMU_BASE 0x05000000 /* GR0 Base */
> > +
> > +/* Cache Coherent Interconnect */
> > +#define CCI_MN_BASE 0x04000000
> > +#define CCI_MN_RNF_NODEID_LIST 0x180
> > +#define CCI_MN_DVM_DOMAIN_CTL 0x200
> > +#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
> > +
> > +#define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000)
> > +#define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000)
> > +#define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000)
> > +#define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000)
> > +#define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000)
> > +#define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000)
> > +
> > +#define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000))
> + 0x10)
> > +#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000))
> + 0x110)
> > +#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000))
> + 0x210)
> > +
> > +/* TZ Protection Controller Definitions */
> > +#define TZPC_BASE 0x02200000
> > +#define TZPCR0SIZE_BASE (TZPC_BASE)
> > +#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
> > +#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
> > +#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
> > +#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
> > +#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
> > +#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
> > +#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
> > +#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
> > +#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
> > +
>
> not sure, are the address of GIC, SMMU, TZPC, RN SoC specific?
>
The GIC, CCI and TZPC macros were ever put in config.h and we decided to move them to immap_lsch3.h.
But we met a lot of header files' mutual #include problems if put in immap_lsch3.h.
So finally we move them to ls2085a_common.h after discussion.
> > /* Errata fixes */
> > #define CONFIG_ARM_ERRATA_828024
> > #define CONFIG_ARM_ERRATA_826974
> >
> > -#include <asm/arch-fsl-lsch3/ls2085a_stream_id.h>
> > -#include <asm/arch-fsl-lsch3/config.h>
> > +#include <asm/arch/ls2085a_stream_id.h>
> > +#include <asm/arch/config.h>
> > #if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
> > #define CONFIG_SYS_HAS_SERDES
> > #endif
> >
> > +/* Link Definitions */
> > +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE +
> 0xfff0)
> > +
> > /* We need architecture specific misc initializations */
> > #define CONFIG_ARCH_MISC_INIT
> >
> > @@ -62,6 +104,7 @@
> >
> > #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving
> */
> >
> > +#define CONFIG_VERY_BIG_RAM
> > #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
> > #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
> > #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
>
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