[U-Boot] [PATCH v4 4/5] arm: dts: socfpga: Increase the spi-max-frequency for QSPI flash

[Chin Liang See]

>From bfc8c2402323353205bc39fa90395417e7ef868c Mon Sep 17 00:00:00 2001
From: Chin Liang See <clsee at altera.com>
Date: Thu, 15 Oct 2015 13:57:42 +0800
Subject: [PATCH v4 4/5] arm: dts: socfpga: Increase the
spi-max-frequency for
 QSPI flash

With a working QSPI calibration, the SCLK can now run up to 100MHz

Signed-off-by: Chin Liang See <clsee at altera.com>
Cc: Dinh Nguyen <dinguyen at opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux at gmail.com>
Cc: Marek Vasut <marex at denx.de>
Cc: Stefan Roese <sr at denx.de>
Cc: Vikas Manocha <vikas.manocha at st.com>
Cc: Jagannadh Teki <jteki at openedev.com>
Cc: Pavel Machek <pavel at denx.de>
Reviewed-by: Marek Vasut <marex at denx.de>
Acked-by: Marek Vasut <marex at denx.de>
Reviewed-by: Jagan Teki <jteki at openedev.com>
---
Changes for v4
- no changes
Changes for v3
- no changes
Changes for v2
- no changes
---
 arch/arm/dts/socfpga_cyclone5_socdk.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts
b/arch/arm/dts/socfpga_cyclone5_socdk.dts
index 9650eb0..04e5695 100644
--- a/arch/arm/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts
@@ -86,7 +86,7 @@
 		#size-cells = <1>;
 		compatible = "n25q00";
 		reg = <0>;      /* chip select */
-		spi-max-frequency = <50000000>;
+		spi-max-frequency = <100000000>;
 		m25p,fast-read;
 		page-size = <256>;
 		block-size = <16>; /* 2^16, 64KB */
-- 
2.2.0