[U-Boot] [PATCH 10/13] x86: Enable mrc cache for bayleybay and minnowmax

[Simon Glass]

On 11 October 2015 at 22:37, Bin Meng <bmeng.cn at gmail.com> wrote:
> Now that we have added MRC cache for Intel FSP and BayTrail codes,
> enable it for all BayTrail boards (Bayley Bay and Minnow Max).
>
> Note it turns out that FSP for Intel Atom E6xx does not produce
> the HOB for NV storage, so we don't have such functionality on
> Intel Crown Bay board.
>
> Signed-off-by: Bin Meng <bmeng.cn at gmail.com>
> ---
>
>  arch/x86/dts/bayleybay.dts  | 6 ++++++
>  arch/x86/dts/minnowmax.dts  | 6 ++++++
>  configs/bayleybay_defconfig | 1 +
>  configs/minnowmax_defconfig | 1 +
>  doc/README.x86              | 1 +
>  5 files changed, 15 insertions(+)

Acked-by: Simon Glass <sjg at chromium.org>