[U-Boot] [PATCH v1 05/12] rockchip: rk3036: Add clock driver

[hl]

Hi Simon,


On 22/10/15 22:07, Simon Glass wrote:
> Hi Lin,
>
> On 20 October 2015 at 20:37, Lin Huang <hl at rock-chips.com> wrote:
>> Add a driver for setting up and modifying the various PLLs, peripheral
>> clocks and mmc clocks on RK3036
>>
>> Signed-off-by: Lin Huang <hl at rock-chips.com>
>> ---
>> Changes in v1:
>> - clean copyright announcement
>>
>>   arch/arm/include/asm/arch-rockchip/cru_rk3036.h |  53 +++
>>   drivers/clk/Makefile                            |   1 +
>>   drivers/clk/clk_rk3036.c                        | 522 ++++++++++++++++++++++++
>>   3 files changed, 576 insertions(+)
>>   create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3036.h
>>   create mode 100644 drivers/clk/clk_rk3036.c
>>
> Acked-by: Simon Glass <sjg at chromium.org>
>
> Please see nit below.
>
>> +static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id,
>> +                        const struct pll_div *div)
>> +{
>> +       int pll_id = rk_pll_id(clk_id);
>> +       struct rk3036_pll *pll = &cru->pll[pll_id];
>> +
>> +       /* All PLLs have same VCO and output frequency range restrictions. */
>> +       uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
>> +       uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
>> +
>> +       debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, postdiv2=%d,\
>> +                vco=%u Hz, output=%u Hz\n",
>> +                       pll, div->fbdiv, div->refdiv, div->postdiv1,
>> +                       div->postdiv2, vco_hz, output_hz);
>> +       assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
>> +              output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
>> +
>> +       /* use interger mode */
> Should that be integer? What does it mean?

     In the rk3036 TRM, you can see:



>
>
>

-- 
Lin Huang

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