[U-Boot] [PATCH v2 7/8] x86: queensbay: Really disable IGD

[Bin Meng]

According to Atom E6xx datasheet, setting VGA Disable (bit17)
of Graphics Controller register (offset 0x50) prevents IGD
(D2:F0) from reporting itself as a VGA display controller
class in the PCI configuration space, and should also prevent
it from responding to VGA legacy memory range and I/O addresses.

However test result shows that with just VGA Disable bit set and
a PCIe graphics card connected to one of the PCIe controllers on
the E6xx, accessing the VGA legacy space still causes system hang.
After a number of attempts, it turns out besides VGA Disable bit,
the SDVO (D3:F0) device should be disabled to make it work.

To simplify, use the Function Disable register (offset 0xc4)
to disable both IGD (D2:F0) and SDVO (D3:F0) devices. Now these
two devices will be completely disabled (invisible in the PCI
configuration space) unless a system reset is performed.

Signed-off-by: Bin Meng <bmeng.cn at gmail.com>
Acked-by: Simon Glass <sjg at chromium.org>
---

Changes in v2: None

 arch/x86/cpu/queensbay/tnc.c              | 26 ++++++++++++++++++++------
 arch/x86/include/asm/arch-queensbay/tnc.h |  7 +++----
 2 files changed, 23 insertions(+), 10 deletions(-)

diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
index 0c02a44..933d189 100644
--- a/arch/x86/cpu/queensbay/tnc.c
+++ b/arch/x86/cpu/queensbay/tnc.c
@@ -25,12 +25,26 @@ static void unprotect_spi_flash(void)
 
 static void __maybe_unused disable_igd(void)
 {
-	u32 gc;
-
-	gc = x86_pci_read_config32(TNC_IGD, IGD_GC);
-	gc &= ~GMS_MASK;
-	gc |= VGA_DISABLE;
-	x86_pci_write_config32(TNC_IGD, IGD_GC, gc);
+	/*
+	 * According to Atom E6xx datasheet, setting VGA Disable (bit17)
+	 * of Graphics Controller register (offset 0x50) prevents IGD
+	 * (D2:F0) from reporting itself as a VGA display controller
+	 * class in the PCI configuration space, and should also prevent
+	 * it from responding to VGA legacy memory range and I/O addresses.
+	 *
+	 * However test result shows that with just VGA Disable bit set and
+	 * a PCIe graphics card connected to one of the PCIe controllers on
+	 * the E6xx, accessing the VGA legacy space still causes system hang.
+	 * After a number of attempts, it turns out besides VGA Disable bit,
+	 * the SDVO (D3:F0) device should be disabled to make it work.
+	 *
+	 * To simplify, use the Function Disable register (offset 0xc4)
+	 * to disable both IGD (D2:F0) and SDVO (D3:F0) devices. Now these
+	 * two devices will be completely disabled (invisible in the PCI
+	 * configuration space) unless a system reset is performed.
+	 */
+	x86_pci_write_config32(TNC_IGD, IGD_FD, FUNC_DISABLE);
+	x86_pci_write_config32(TNC_SDVO, IGD_FD, FUNC_DISABLE);
 }
 
 int arch_cpu_init(void)
diff --git a/arch/x86/include/asm/arch-queensbay/tnc.h b/arch/x86/include/asm/arch-queensbay/tnc.h
index 2365394..8477d92 100644
--- a/arch/x86/include/asm/arch-queensbay/tnc.h
+++ b/arch/x86/include/asm/arch-queensbay/tnc.h
@@ -7,10 +7,9 @@
 #ifndef _X86_ARCH_TNC_H_
 #define _X86_ARCH_TNC_H_
 
-/* IGD Control Register */
-#define IGD_GC		0x50
-#define VGA_DISABLE	0x00020000
-#define GMS_MASK	0x00700000
+/* IGD Function Disable Register */
+#define IGD_FD		0xc4
+#define FUNC_DISABLE	0x00000001
 
 /* Memory BAR Enable */
 #define MEM_BAR_EN	0x00000001
-- 
1.8.2.1