[U-Boot] [PATCH v4 06/24] spi: cadence_qspi_apb: Use BIT macro

[Vikas MANOCHA]

Thanks Jagan for this patch.

Acked-by: vikas.manocha at st.com

Rgds,
Vikas

> -----Original Message-----
> From: Jagan Teki [mailto:jteki at openedev.com]
> Sent: Thursday, October 22, 2015 1:50 PM
> To: u-boot at lists.denx.de
> Cc: Jagan Teki; Stefan Roese; Vikas MANOCHA; Marek Vasut
> Subject: [PATCH v4 06/24] spi: cadence_qspi_apb: Use BIT macro
> 
> Replace numerical bit shift with BIT macro in cadence_qspi_apb
> 
> :%s/(1 << nr)/BIT(nr)/g
> where nr = 0, 1, 2 .... 31
> 
> Cc: Stefan Roese <sr at denx.de>
> Cc: Vikas Manocha <vikas.manocha at st.com>
> Cc: Marek Vasut <marex at denx.de>
> Signed-off-by: Jagan Teki <jteki at openedev.com>
> ---
>  drivers/spi/cadence_qspi_apb.c | 28 ++++++++++++++--------------
>  1 file changed, 14 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/spi/cadence_qspi_apb.c
> b/drivers/spi/cadence_qspi_apb.c index d053407..7786dd6 100644
> --- a/drivers/spi/cadence_qspi_apb.c
> +++ b/drivers/spi/cadence_qspi_apb.c
> @@ -58,10 +58,10 @@
>  #define	CQSPI_REG_CONFIG			0x00
>  #define	CQSPI_REG_CONFIG_CLK_POL_LSB		1
>  #define	CQSPI_REG_CONFIG_CLK_PHA_LSB		2
> -#define	CQSPI_REG_CONFIG_ENABLE_MASK		(1 << 0)
> -#define	CQSPI_REG_CONFIG_DIRECT_MASK		(1 << 7)
> -#define	CQSPI_REG_CONFIG_DECODE_MASK		(1 << 9)
> -#define	CQSPI_REG_CONFIG_XIP_IMM_MASK		(1 << 18)
> +#define	CQSPI_REG_CONFIG_ENABLE_MASK		BIT(0)
> +#define	CQSPI_REG_CONFIG_DIRECT_MASK		BIT(7)
> +#define	CQSPI_REG_CONFIG_DECODE_MASK		BIT(9)
> +#define	CQSPI_REG_CONFIG_XIP_IMM_MASK		BIT(18)
>  #define	CQSPI_REG_CONFIG_CHIPSELECT_LSB		10
>  #define	CQSPI_REG_CONFIG_BAUD_LSB		19
>  #define	CQSPI_REG_CONFIG_IDLE_LSB		31
> @@ -122,18 +122,18 @@
>  #define	CQSPI_REG_IRQMASK			0x44
> 
>  #define	CQSPI_REG_INDIRECTRD			0x60
> -#define	CQSPI_REG_INDIRECTRD_START_MASK		(1 <<
> 0)
> -#define	CQSPI_REG_INDIRECTRD_CANCEL_MASK	(1 << 1)
> -#define	CQSPI_REG_INDIRECTRD_INPROGRESS_MASK	(1 << 2)
> -#define	CQSPI_REG_INDIRECTRD_DONE_MASK		(1 <<
> 5)
> +#define	CQSPI_REG_INDIRECTRD_START_MASK		BIT(0)
> +#define	CQSPI_REG_INDIRECTRD_CANCEL_MASK	BIT(1)
> +#define	CQSPI_REG_INDIRECTRD_INPROGRESS_MASK	BIT(2)
> +#define	CQSPI_REG_INDIRECTRD_DONE_MASK		BIT(5)
> 
>  #define	CQSPI_REG_INDIRECTRDWATERMARK		0x64
>  #define	CQSPI_REG_INDIRECTRDSTARTADDR		0x68
>  #define	CQSPI_REG_INDIRECTRDBYTES		0x6C
> 
>  #define	CQSPI_REG_CMDCTRL			0x90
> -#define	CQSPI_REG_CMDCTRL_EXECUTE_MASK		(1 <<
> 0)
> -#define	CQSPI_REG_CMDCTRL_INPROGRESS_MASK	(1 << 1)
> +#define	CQSPI_REG_CMDCTRL_EXECUTE_MASK		BIT(0)
> +#define	CQSPI_REG_CMDCTRL_INPROGRESS_MASK	BIT(1)
>  #define	CQSPI_REG_CMDCTRL_DUMMY_LSB		7
>  #define	CQSPI_REG_CMDCTRL_WR_BYTES_LSB		12
>  #define	CQSPI_REG_CMDCTRL_WR_EN_LSB		15
> @@ -149,10 +149,10 @@
>  #define	CQSPI_REG_CMDCTRL_OPCODE_MASK		0xFF
> 
>  #define	CQSPI_REG_INDIRECTWR			0x70
> -#define	CQSPI_REG_INDIRECTWR_START_MASK		(1 <<
> 0)
> -#define	CQSPI_REG_INDIRECTWR_CANCEL_MASK	(1 << 1)
> -#define	CQSPI_REG_INDIRECTWR_INPROGRESS_MASK	(1 <<
> 2)
> -#define	CQSPI_REG_INDIRECTWR_DONE_MASK		(1 <<
> 5)
> +#define	CQSPI_REG_INDIRECTWR_START_MASK		BIT(0)
> +#define	CQSPI_REG_INDIRECTWR_CANCEL_MASK	BIT(1)
> +#define	CQSPI_REG_INDIRECTWR_INPROGRESS_MASK	BIT(2)
> +#define	CQSPI_REG_INDIRECTWR_DONE_MASK		BIT(5)
> 
>  #define	CQSPI_REG_INDIRECTWRWATERMARK		0x74
>  #define	CQSPI_REG_INDIRECTWRSTARTADDR		0x78
> --
> 1.9.1