[U-Boot] [PATCH v4 18/24] spi: cadence_qspi_apb: Use GENMASK

[Fabio Estevam]

Jagan,

On Fri, Oct 23, 2015 at 3:17 PM, Jagan Teki <jteki at openedev.com> wrote:
> On 23 October 2015 at 02:55, Tom Rini <trini at konsulko.com> wrote:
>> On Thu, Oct 22, 2015 at 07:10:17PM -0200, Fabio Estevam wrote:
>>> On Thu, Oct 22, 2015 at 6:50 PM, Jagan Teki <jteki at openedev.com> wrote:
>>>
>>> >         reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
>>> > @@ -719,7 +719,7 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
>>> >  #if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD)
>>> >                 writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);
>>> >  #else
>>> > -               writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);
>>> > +               writel(GENMASK(7, 0), plat->regbase + CQSPI_REG_MODE_BIT);
>>>
>>> Is the 0xFF really a mask here? It seems it is just writing 0xFF to
>>> the register directly without any masking operation.

Your quoting style is a bit odd.

You are replying to my message in Tom's reply. This is confusing.

> As register got initialized to all 1's like masking all to set may be
> we can add a macro like MODE_BIT_MASK and then will assign GENMASK to
> that.

Sorry, bu this sentence is hard to parse.

Anyway, this change is only making the code harder to read.