[U-Boot] [PATCH 2/4] ebony: Drop
Bin Meng
bmeng.cn at gmail.com
Sun Oct 25 03:43:08 CET 2015
On Sun, Oct 25, 2015 at 5:24 AM, Tom Rini <trini at konsulko.com> wrote:
> This board has not compiled for me for quite some time due to size
> constraints, remove.
>
> Cc: Stefan Roese <sr at denx.de>
> Signed-off-by: Tom Rini <trini at konsulko.com>
> ---
Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
> board/amcc/ebony/Kconfig | 16 ----
> board/amcc/ebony/MAINTAINERS | 6 --
> board/amcc/ebony/Makefile | 9 ---
> board/amcc/ebony/README | 136 ---------------------------------
> board/amcc/ebony/config.mk | 16 ----
> board/amcc/ebony/ebony.c | 151 ------------------------------------
> board/amcc/ebony/flash.c | 155 -------------------------------------
> board/amcc/ebony/init.S | 41 ----------
> configs/ebony_defconfig | 3 -
> doc/README.scrapyard | 1 +
> include/configs/ebony.h | 174 ------------------------------------------
> 11 files changed, 1 insertion(+), 707 deletions(-)
> delete mode 100644 board/amcc/ebony/Kconfig
> delete mode 100644 board/amcc/ebony/MAINTAINERS
> delete mode 100644 board/amcc/ebony/Makefile
> delete mode 100644 board/amcc/ebony/README
> delete mode 100644 board/amcc/ebony/config.mk
> delete mode 100644 board/amcc/ebony/ebony.c
> delete mode 100644 board/amcc/ebony/flash.c
> delete mode 100644 board/amcc/ebony/init.S
> delete mode 100644 configs/ebony_defconfig
> delete mode 100644 include/configs/ebony.h
>
> diff --git a/board/amcc/ebony/Kconfig b/board/amcc/ebony/Kconfig
> deleted file mode 100644
> index ba73148..0000000
> --- a/board/amcc/ebony/Kconfig
> +++ /dev/null
> @@ -1,16 +0,0 @@
> -if TARGET_EBONY
> -
> -config SYS_BOARD
> - default "ebony"
> -
> -config SYS_VENDOR
> - default "amcc"
> -
> -config SYS_CONFIG_NAME
> - default "ebony"
> -
> -config DISPLAY_BOARDINFO
> - bool
> - default y
> -
> -endif
> diff --git a/board/amcc/ebony/MAINTAINERS b/board/amcc/ebony/MAINTAINERS
> deleted file mode 100644
> index bc62851..0000000
> --- a/board/amcc/ebony/MAINTAINERS
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -EBONY BOARD
> -M: Stefan Roese <sr at denx.de>
> -S: Maintained
> -F: board/amcc/ebony/
> -F: include/configs/ebony.h
> -F: configs/ebony_defconfig
> diff --git a/board/amcc/ebony/Makefile b/board/amcc/ebony/Makefile
> deleted file mode 100644
> index 5876486..0000000
> --- a/board/amcc/ebony/Makefile
> +++ /dev/null
> @@ -1,9 +0,0 @@
> -#
> -# (C) Copyright 2002-2006
> -# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> -#
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -
> -obj-y = ebony.o flash.o
> -extra-y += init.o
> diff --git a/board/amcc/ebony/README b/board/amcc/ebony/README
> deleted file mode 100644
> index 4df00b3..0000000
> --- a/board/amcc/ebony/README
> +++ /dev/null
> @@ -1,136 +0,0 @@
> - AMCC Ebony Board
> -
> - Last Update: September 12, 2002
> -=======================================================================
> -
> -This file contains some handy info regarding U-Boot and the AMCC
> -Ebony evaluation board. See the README.ppc440 for additional
> -information.
> -
> -
> -SWITCH SETTINGS & JUMPERS
> -==========================
> -
> -Here's what I've been using successfully. If you feel inclined to
> -change things ... please read the docs!
> -
> -DIPSW U46 U80
> -------------------------
> -SW 1 off on
> -SW 2 on on
> -SW 3 on on
> -SW 4 off on
> -SW 5 on off
> -SW 6 on on
> -SW 7 on off
> -SW 8 on off
> -
> -J41: strapped
> -J42: open
> -
> -All others are factory default.
> -
> -
> -I2C probe
> -=====================
> -
> -The i2c utilities have been tested on both Rev B. and Rev C. and
> -look good. The CONFIG_SYS_I2C_NOPROBES macro is defined to prevent
> -probing the CDCV850 clock controller at address 0x69 (since reading
> -it causes the i2c implementation to misbehave. The output of
> -'i2c probe' should look like this (assuming you are only using a single
> -SO-DIMM:
> -
> -=> i2c probe
> -Valid chip addresses: 50 53 54
> -Excluded chip addresses: 69
> -
> -
> -GETTING OUT OF I2C TROUBLE
> -===========================
> -
> -If you're like me ... you may have screwed up your bootstrap serial
> -eeprom ... or worse, your SPD eeprom when experimenting with the
> -i2c commands. If so, here are some ideas on how to get out of
> -trouble:
> -
> -Serial bootstrap eeprom corruption:
> ------------------------------------
> -Power down the board and set the following straps:
> -
> -J41 - open
> -J42 - strapped
> -
> -This will select the default sys0 and sys1 settings (the serial
> -eeproms are not used). Then power up the board and fix the serial
> -eeprom using the 'i2c mm' command. Here are the values I currently
> -use:
> -
> -=> i2c md 50 0 10
> -0000: bf a2 04 01 ae 94 11 00 00 00 00 00 00 00 00 00 ................
> -
> -=> i2c md 54 0 10
> -0000: 8f b3 24 01 4d 14 11 00 00 00 00 00 00 00 00 00 ..$.M...........
> -
> -Once you have the eeproms set correctly change the
> -J41/J42 straps as you desire.
> -
> -SPD eeprom corruption:
> -------------------------
> -I've corrupted the SPD eeprom several times ... perhaps too much coffee
> -and not enough presence of mind ;-). By default, the ebony code uses
> -the SPD to initialize the DDR SDRAM control registers. So if the SPD
> -eeprom is corrupted, U-Boot will never get into ram. Here's how I got
> -out of this situation:
> -
> -0. First, _before_ playing with the i2c utilities, do an 'i2c probe', then
> -use 'i2c md' to capture the various device contents to a file. Some day
> -you may be glad you did this ... trust me :-). Otherwise try the
> -following:
> -
> -1. In the include/configs/EBONY.h file find the line that defines
> -the CONFIG_SPD_EEPROM macro and undefine it. E.g:
> -
> -#undef CONFIG_SPD_EEPROM
> -
> -This will make the code use default SDRAM control register
> -settings without using the SPD eeprom.
> -
> -2. Rebuild U-Boot
> -
> -3. Load the new U-Boot image and reboot ebony.
> -
> -4. Repair the SPD eeprom using the 'i2c mm' command. Here's the eeprom
> -contents that work with the default SO-DIMM that comes with the
> -ebony board (micron 8VDDT164AG-265A1). Note: these are probably
> -_not_ the factory settings ... but they work.
> -
> -=> i2c md 53 0 10 80
> -0000: 80 08 07 0c 0a 01 40 00 04 75 75 00 80 08 00 01 ...... at ..uu.....
> -0010: 0e 04 0c 01 02 20 00 a0 75 00 00 50 3c 50 2d 20 ..... ..u..P<P-
> -0020: 90 90 50 50 00 00 00 00 00 41 4b 34 32 75 00 00 ..PP.....AK42u..
> -0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 9c ................
> -0040: 2c 00 00 00 00 00 00 00 08 38 56 44 44 54 31 36 ,........8VDDT16
> -0050: 36 34 41 47 2d 32 36 35 41 31 20 01 00 01 2c 63 64AG-265A1 ...,c
> -0060: 22 25 ab 00 00 00 00 00 00 00 00 00 00 00 00 00 "%..............
> -0070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
> -
> -
> -PCI DOUBLE-ENUMERATION WOES
> -===========================
> -
> -If you're not using PCI-X cards and are simply using 32-bit and/or
> -33 MHz cards via extenders and the like, you may notice that the
> -initial pci scan reports various devices twice ... and configuration
> -does not succeed (one or more devices are enumerated twice). To correct
> -this we replaced the 2K ohm resistor on the IDSEL line(s) with a
> -22 ohm resistor and the problem went away. This change hasn't broken
> -anything yet -- use at your own risk.
> -
> -We never tested anything other than 33 MHz/32-bit cards. If you have
> -the chance to do this, please let me know how things turn out :-)
> -
> -
> -Regards,
> ---Scott
> -<smcnutt at artesyncp.com>
> diff --git a/board/amcc/ebony/config.mk b/board/amcc/ebony/config.mk
> deleted file mode 100644
> index f18b097..0000000
> --- a/board/amcc/ebony/config.mk
> +++ /dev/null
> @@ -1,16 +0,0 @@
> -#
> -# (C) Copyright 2002
> -# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> -#
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -
> -PLATFORM_CPPFLAGS += -DCONFIG_440=1
> -
> -ifeq ($(debug),1)
> -PLATFORM_CPPFLAGS += -DDEBUG
> -endif
> -
> -ifeq ($(dbcr),1)
> -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
> -endif
> diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c
> deleted file mode 100644
> index eb42448..0000000
> --- a/board/amcc/ebony/ebony.c
> +++ /dev/null
> @@ -1,151 +0,0 @@
> -/*
> - * Copyright (C) 2002 Scott McNutt <smcnutt at artesyncp.com>
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#include <common.h>
> -#include <asm/processor.h>
> -#include <spd_sdram.h>
> -
> -#define BOOT_SMALL_FLASH 32 /* 00100000 */
> -#define FLASH_ONBD_N 2 /* 00000010 */
> -#define FLASH_SRAM_SEL 1 /* 00000001 */
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -long int fixed_sdram(void);
> -
> -int board_early_init_f(void)
> -{
> - uint reg;
> - unsigned char *fpga_base = (unsigned char *)CONFIG_SYS_FPGA_BASE;
> - unsigned char status;
> -
> - /*--------------------------------------------------------------------
> - * Setup the external bus controller/chip selects
> - *-------------------------------------------------------------------*/
> - mtdcr(EBC0_CFGADDR, EBC0_CFG);
> - reg = mfdcr(EBC0_CFGDATA);
> - mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */
> -
> - mtebc(PB1AP, 0x02815480); /* NVRAM/RTC */
> - mtebc(PB1CR, 0x48018000); /* BA=0x480 1MB R/W 8-bit */
> - mtebc(PB7AP, 0x01015280); /* FPGA registers */
> - mtebc(PB7CR, 0x48318000); /* BA=0x483 1MB R/W 8-bit */
> -
> - /* read FPGA_REG0 and set the bus controller */
> - status = *fpga_base;
> - if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) {
> - mtebc(PB0AP, 0x9b015480); /* FLASH/SRAM */
> - mtebc(PB0CR, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */
> - mtebc(PB2AP, 0x9b015480); /* 4MB FLASH */
> - mtebc(PB2CR, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */
> - } else {
> - mtebc(PB0AP, 0x9b015480); /* 4MB FLASH */
> - mtebc(PB0CR, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */
> -
> - /* set CS2 if FLASH_ONBD_N == 0 */
> - if (!(status & FLASH_ONBD_N)) {
> - mtebc(PB2AP, 0x9b015480); /* FLASH/SRAM */
> - mtebc(PB2CR, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */
> - }
> - }
> -
> - /*--------------------------------------------------------------------
> - * Setup the interrupt controller polarities, triggers, etc.
> - *-------------------------------------------------------------------*/
> - mtdcr(UIC0SR, 0xffffffff); /* clear all */
> - mtdcr(UIC0ER, 0x00000000); /* disable all */
> - mtdcr(UIC0CR, 0x00000009); /* SMI & UIC1 crit are critical */
> - mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
> - mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
> - mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
> - mtdcr(UIC0SR, 0xffffffff); /* clear all */
> -
> - mtdcr(UIC1SR, 0xffffffff); /* clear all */
> - mtdcr(UIC1ER, 0x00000000); /* disable all */
> - mtdcr(UIC1CR, 0x00000000); /* all non-critical */
> - mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
> - mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
> - mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
> - mtdcr(UIC1SR, 0xffffffff); /* clear all */
> -
> - return 0;
> -}
> -
> -int checkboard(void)
> -{
> - char buf[64];
> - int i = getenv_f("serial#", buf, sizeof(buf));
> -
> - printf("Board: Ebony - AMCC PPC440GP Evaluation Board");
> - if (i > 0) {
> - puts(", serial# ");
> - puts(buf);
> - }
> - putc('\n');
> -
> - return (0);
> -}
> -
> -phys_size_t initdram(int board_type)
> -{
> - long dram_size = 0;
> -
> -#if defined(CONFIG_SPD_EEPROM)
> - dram_size = spd_sdram();
> -#else
> - dram_size = fixed_sdram();
> -#endif
> - return dram_size;
> -}
> -
> -#if !defined(CONFIG_SPD_EEPROM)
> -/*************************************************************************
> - * fixed sdram init -- doesn't use serial presence detect.
> - *
> - * Assumes: 128 MB, non-ECC, non-registered
> - * PLB @ 133 MHz
> - *
> - ************************************************************************/
> -long int fixed_sdram(void)
> -{
> - uint reg;
> -
> - /*--------------------------------------------------------------------
> - * Setup some default
> - *------------------------------------------------------------------*/
> - mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
> - mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
> - mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
> - mtsdram(SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */
> - mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
> -
> - /*--------------------------------------------------------------------
> - * Setup for board-specific specific mem
> - *------------------------------------------------------------------*/
> - /*
> - * Following for CAS Latency = 2.5 @ 133 MHz PLB
> - */
> - mtsdram(SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
> - mtsdram(SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
> - /* RA=10 RD=3 */
> - mtsdram(SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
> - mtsdram(SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
> - mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */
> - udelay(400); /* Delay 200 usecs (min) */
> -
> - /*--------------------------------------------------------------------
> - * Enable the controller, then wait for DCEN to complete
> - *------------------------------------------------------------------*/
> - mtsdram(SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
> - for (;;) {
> - mfsdram(SDRAM0_MCSTS, reg);
> - if (reg & 0x80000000)
> - break;
> - }
> -
> - return (128 * 1024 * 1024); /* 128 MB */
> -}
> -#endif /* !defined(CONFIG_SPD_EEPROM) */
> diff --git a/board/amcc/ebony/flash.c b/board/amcc/ebony/flash.c
> deleted file mode 100644
> index 5740a56..0000000
> --- a/board/amcc/ebony/flash.c
> +++ /dev/null
> @@ -1,155 +0,0 @@
> -/*
> - * (C) Copyright 2002
> - * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> - *
> - * (C) Copyright 2002 Jun Gu <jung at artesyncp.com>
> - * Add support for Am29F016D and dynamic switch setting.
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -/*
> - * Modified 4/5/2001
> - * Wait for completion of each sector erase command issued
> - * 4/5/2001
> - * Chris Hallinan - DS4.COM, Inc. - clh at net1plus.com
> - */
> -
> -#include <common.h>
> -#include <asm/ppc4xx.h>
> -#include <asm/processor.h>
> -#include <asm/io.h>
> -
> -#undef DEBUG
> -#ifdef DEBUG
> -#define DEBUGF(x...) printf(x)
> -#else
> -#define DEBUGF(x...)
> -#endif /* DEBUG */
> -
> -#define BOOT_SMALL_FLASH 32 /* 00100000 */
> -#define FLASH_ONBD_N 2 /* 00000010 */
> -#define FLASH_SRAM_SEL 1 /* 00000001 */
> -
> -#define BOOT_SMALL_FLASH_VAL 4
> -#define FLASH_ONBD_N_VAL 2
> -#define FLASH_SRAM_SEL_VAL 1
> -
> -static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = {
> - {0xffc00000, 0xffe00000, 0xff880000}, /* 0:000: configuraton 3 */
> - {0xffc00000, 0xffe00000, 0xff800000}, /* 1:001: configuraton 4 */
> - {0xffc00000, 0xffe00000, 0x00000000}, /* 2:010: configuraton 7 */
> - {0xffc00000, 0xffe00000, 0x00000000}, /* 3:011: configuraton 8 */
> - {0xff800000, 0xffa00000, 0xfff80000}, /* 4:100: configuraton 1 */
> - {0xff800000, 0xffa00000, 0xfff00000}, /* 5:101: configuraton 2 */
> - {0xffc00000, 0xffe00000, 0x00000000}, /* 6:110: configuraton 5 */
> - {0xffc00000, 0xffe00000, 0x00000000} /* 7:111: configuraton 6 */
> -};
> -
> -/*
> - * include common flash code (for amcc boards)
> - */
> -#include "../common/flash.c"
> -
> -/*-----------------------------------------------------------------------
> - * Functions
> - */
> -static ulong flash_get_size(vu_long * addr, flash_info_t * info);
> -
> -/*
> - * Override the weak default mapping function with a board specific one
> - */
> -u32 flash_get_bank_size(int cs, int idx)
> -{
> - u8 reg = in_8((void *)CONFIG_SYS_FPGA_BASE);
> -
> - if ((reg & BOOT_SMALL_FLASH) && !(reg & FLASH_ONBD_N)) {
> - /*
> - * cs0: small flash (512KiB)
> - * cs2: 2 * big flash (2 * 2MiB)
> - */
> - if (cs == 0)
> - return flash_info[2].size;
> - if (cs == 2)
> - return flash_info[0].size + flash_info[1].size;
> - } else {
> - /*
> - * cs0: 2 * big flash (2 * 2MiB)
> - * cs2: small flash (512KiB)
> - */
> - if (cs == 0)
> - return flash_info[0].size + flash_info[1].size;
> - if (cs == 2)
> - return flash_info[2].size;
> - }
> -
> - return 0;
> -}
> -
> -unsigned long flash_init(void)
> -{
> - unsigned long total_b = 0;
> - unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
> - unsigned char *fpga_base = (unsigned char *)CONFIG_SYS_FPGA_BASE;
> - unsigned char switch_status;
> - unsigned short index = 0;
> - int i;
> -
> - /* read FPGA base register FPGA_REG0 */
> - switch_status = *fpga_base;
> -
> - /* check the bitmap of switch status */
> - if (switch_status & BOOT_SMALL_FLASH) {
> - index += BOOT_SMALL_FLASH_VAL;
> - }
> - if (switch_status & FLASH_ONBD_N) {
> - index += FLASH_ONBD_N_VAL;
> - }
> - if (switch_status & FLASH_SRAM_SEL) {
> - index += FLASH_SRAM_SEL_VAL;
> - }
> -
> - DEBUGF("\n");
> - DEBUGF("FLASH: Index: %d\n", index);
> -
> - /* Init: no FLASHes known */
> - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
> - flash_info[i].flash_id = FLASH_UNKNOWN;
> - flash_info[i].sector_count = -1;
> - flash_info[i].size = 0;
> -
> - /* check whether the address is 0 */
> - if (flash_addr_table[index][i] == 0) {
> - continue;
> - }
> -
> - /* call flash_get_size() to initialize sector address */
> - size_b[i] = flash_get_size((vu_long *)
> - flash_addr_table[index][i],
> - &flash_info[i]);
> - flash_info[i].size = size_b[i];
> - if (flash_info[i].flash_id == FLASH_UNKNOWN) {
> - printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
> - i, size_b[i], size_b[i] << 20);
> - flash_info[i].sector_count = -1;
> - flash_info[i].size = 0;
> - }
> -
> - /* Monitor protection ON by default */
> - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
> - CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
> - &flash_info[2]);
> -#ifdef CONFIG_ENV_IS_IN_FLASH
> - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
> - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
> - &flash_info[2]);
> - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
> - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
> - &flash_info[2]);
> -#endif
> -
> - total_b += flash_info[i].size;
> - }
> -
> - return total_b;
> -}
> diff --git a/board/amcc/ebony/init.S b/board/amcc/ebony/init.S
> deleted file mode 100644
> index 904e648..0000000
> --- a/board/amcc/ebony/init.S
> +++ /dev/null
> @@ -1,41 +0,0 @@
> -/*
> -* Copyright (C) 2002 Scott McNutt <smcnutt at artesyncp.com>
> - * SPDX-License-Identifier: GPL-2.0+
> -*/
> -
> -#include <ppc_asm.tmpl>
> -#include <config.h>
> -#include <asm/mmu.h>
> -#include <asm/ppc4xx.h>
> -
> -/**************************************************************************
> - * TLB TABLE
> - *
> - * This table is used by the cpu boot code to setup the initial tlb
> - * entries. Rather than make broad assumptions in the cpu source tree,
> - * this table lets each board set things up however they like.
> - *
> - * Pointer to the table is returned in r1
> - *
> - *************************************************************************/
> -
> - .section .bootpg,"ax"
> - .globl tlbtab
> -
> -tlbtab:
> - tlbtab_start
> -
> - tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
> -
> - /*
> - * TLB entries for SDRAM are not needed on this platform.
> - * They are dynamically generated in the SPD DDR(2) detection
> - * routine.
> - */
> -
> - tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
> - tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX)
> - tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX)
> - tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG)
> - tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG)
> - tlbtab_end
> diff --git a/configs/ebony_defconfig b/configs/ebony_defconfig
> deleted file mode 100644
> index db93555..0000000
> --- a/configs/ebony_defconfig
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -CONFIG_PPC=y
> -CONFIG_4xx=y
> -CONFIG_TARGET_EBONY=y
> diff --git a/doc/README.scrapyard b/doc/README.scrapyard
> index 5ef6c4e..973798d 100644
> --- a/doc/README.scrapyard
> +++ b/doc/README.scrapyard
> @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
>
> Board Arch CPU Commit Removed Last known maintainer/contact
> =================================================================================================
> +ebony powerpc ppc4xx - - Stefan Roese <sr at denx.de>
> taihu powerpc ppc4xx - - John Otken <jotken at softadvances.com>
> lcd4_lwmon5 powerpc ppc4xx b6b5e394 2015-10-02 Stefan Roese <sr at denx.de>
> da830evm arm arm926ejs d7e8b2b9 2015-09-12 Nick Thompson <nick.thompson at gefanuc.com>
> diff --git a/include/configs/ebony.h b/include/configs/ebony.h
> deleted file mode 100644
> index 3f0ad69..0000000
> --- a/include/configs/ebony.h
> +++ /dev/null
> @@ -1,174 +0,0 @@
> -/*
> - * (C) Copyright 2002 Scott McNutt <smcnutt at artesyncp.com>
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -/************************************************************************
> - * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony)
> - ***********************************************************************/
> -
> -#ifndef __CONFIG_H
> -#define __CONFIG_H
> -
> -/*-----------------------------------------------------------------------
> - * High Level Configuration Options
> - *----------------------------------------------------------------------*/
> -#define CONFIG_EBONY 1 /* Board is ebony */
> -#define CONFIG_440GP 1 /* Specifc GP support */
> -#define CONFIG_440 1 /* ... PPC440 family */
> -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
> -#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
> -
> -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
> -
> -/*
> - * Include common defines/options for all AMCC eval boards
> - */
> -#define CONFIG_HOSTNAME ebony
> -#include "amcc-common.h"
> -
> -/*
> - * Define here the location of the environment variables (FLASH or NVRAM).
> - * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
> - * supported for backward compatibility.
> - */
> -#if 1
> -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
> -#else
> -#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
> -#endif
> -
> -/*-----------------------------------------------------------------------
> - * Base addresses -- Note these are effective addresses where the
> - * actual resources get mapped (not physical addresses)
> - *----------------------------------------------------------------------*/
> -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
> -#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH */
> -#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
> -#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
> -#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
> -
> -#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
> -#define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08300000)
> -
> -/*-----------------------------------------------------------------------
> - * Initial RAM & stack pointer (placed in internal SRAM)
> - *----------------------------------------------------------------------*/
> -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
> -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
> -
> -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
> -
> -/*-----------------------------------------------------------------------
> - * Serial Port
> - *----------------------------------------------------------------------*/
> -#define CONFIG_CONS_INDEX 1 /* Use UART0 */
> -#define CONFIG_SYS_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */
> -
> -/*-----------------------------------------------------------------------
> - * NVRAM/RTC
> - *
> - * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
> - * The DS1743 code assumes this condition (i.e. -- it assumes the base
> - * address for the RTC registers is:
> - *
> - * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
> - *
> - *----------------------------------------------------------------------*/
> -#define CONFIG_SYS_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */
> -#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
> -
> -#ifdef CONFIG_ENV_IS_IN_NVRAM
> -#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
> -#define CONFIG_ENV_ADDR \
> - (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)
> -#endif /* CONFIG_ENV_IS_IN_NVRAM */
> -
> -/*-----------------------------------------------------------------------
> - * FLASH related
> - *----------------------------------------------------------------------*/
> -#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* number of banks */
> -#define CONFIG_SYS_MAX_FLASH_SECT 32 /* sectors per device */
> -
> -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
> -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
> -
> -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
> -
> -#define CONFIG_SYS_FLASH_ADDR0 0x5555
> -#define CONFIG_SYS_FLASH_ADDR1 0x2aaa
> -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char
> -
> -#ifdef CONFIG_ENV_IS_IN_FLASH
> -#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
> -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
> -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
> -
> -/* Address and size of Redundant Environment Sector */
> -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
> -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
> -#endif /* CONFIG_ENV_IS_IN_FLASH */
> -
> -/*-----------------------------------------------------------------------
> - * DDR SDRAM
> - *----------------------------------------------------------------------*/
> -#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
> -#define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */
> -#define CONFIG_PROG_SDRAM_TLB 1 /* setup SDRAM TLB's dynamically*/
> -
> -/*-----------------------------------------------------------------------
> - * I2C
> - *----------------------------------------------------------------------*/
> -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
> -
> -#define CONFIG_SYS_I2C_MULTI_EEPROMS
> -#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
> -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
> -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
> -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
> -
> -/*
> - * Default environment variables
> - */
> -#define CONFIG_EXTRA_ENV_SETTINGS \
> - CONFIG_AMCC_DEF_ENV \
> - CONFIG_AMCC_DEF_ENV_POWERPC \
> - CONFIG_AMCC_DEF_ENV_PPC_OLD \
> - CONFIG_AMCC_DEF_ENV_NOR_UPD \
> - "kernel_addr=ff800000\0" \
> - "ramdisk_addr=ff810000\0" \
> - ""
> -
> -#define CONFIG_PHY_ADDR 8 /* PHY address */
> -#define CONFIG_HAS_ETH0
> -#define CONFIG_HAS_ETH1
> -#define CONFIG_PHY1_ADDR 9 /* EMAC1 PHY address */
> -
> -/*
> - * Commands additional to the ones defined in amcc-common.h
> - */
> -#define CONFIG_CMD_DATE
> -#define CONFIG_CMD_PCI
> -#define CONFIG_CMD_SDRAM
> -#define CONFIG_CMD_SNTP
> -
> -/*-----------------------------------------------------------------------
> - * PCI stuff
> - *-----------------------------------------------------------------------
> - */
> -/* General PCI */
> -#define CONFIG_PCI /* include pci support */
> -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
> -#define CONFIG_PCI_PNP /* do pci plug-and-play */
> -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
> -#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
> -
> -/* Board-specific PCI */
> -#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
> -
> -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
> -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
> -
> -#endif /* __CONFIG_H */
> --
> 1.7.9.5
>
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