[U-Boot] [PATCH v5 01/23] spi: zynq_[q]spi: Use BIT macro

[Siva Durga Prasad Paladugu]

> -----Original Message-----
> From: Jagan Teki [mailto:jteki at openedev.com]
> Sent: Saturday, October 24, 2015 9:09 AM
> To: u-boot at lists.denx.de
> Cc: Jagan Teki; Siva Durga Prasad Paladugu; Michal Simek
> Subject: [PATCH v5 01/23] spi: zynq_[q]spi: Use BIT macro
> 
> Used BIT macro on zynq_spi.c and zynq_qspi.c
> 
> :%s/(1 << nr)/BIT(nr)/g
> where nr = 0, 1, 2 .... 31
> 
> Cc: Siva Durga Prasad Paladugu <sivadur at xilinx.com>
> Cc: Michal Simek <michal.simek at xilinx.com>
> Reviewed-by: Tom Rini <trini at konsulko.com>
> Signed-off-by: Jagan Teki <jteki at openedev.com>
   Acked-by: Siva Durga Prasad Paladugu <sivadur at xilinx.com>
> ---
>  drivers/spi/zynq_qspi.c | 20 ++++++++++----------  drivers/spi/zynq_spi.c  |
> 16 ++++++++--------
>  2 files changed, 18 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c index
> 8aa61d7..dd530a1 100644
> --- a/drivers/spi/zynq_qspi.c
> +++ b/drivers/spi/zynq_qspi.c
> @@ -16,20 +16,20 @@
>  DECLARE_GLOBAL_DATA_PTR;
> 
>  /* zynq qspi register bit masks ZYNQ_QSPI_<REG>_<BIT>_MASK */
> -#define ZYNQ_QSPI_CR_IFMODE_MASK	(1 << 31)	/* Flash
> intrface mode*/
> -#define ZYNQ_QSPI_CR_MSA_MASK		(1 << 15)	/* Manual
> start enb */
> -#define ZYNQ_QSPI_CR_MCS_MASK		(1 << 14)	/* Manual
> chip select */
> -#define ZYNQ_QSPI_CR_PCS_MASK		(1 << 10)	/* Peri chip
> select */
> +#define ZYNQ_QSPI_CR_IFMODE_MASK	BIT(31)	/* Flash intrface
> mode*/
> +#define ZYNQ_QSPI_CR_MSA_MASK		BIT(15)	/* Manual start enb
> */
> +#define ZYNQ_QSPI_CR_MCS_MASK		BIT(14)	/* Manual chip select
> */
> +#define ZYNQ_QSPI_CR_PCS_MASK		BIT(10)	/* Peri chip select */
>  #define ZYNQ_QSPI_CR_FW_MASK		(0x3 << 6)	/* FIFO width
> */
>  #define ZYNQ_QSPI_CR_SS_MASK		(0xF << 10)	/* Slave
> Select */
>  #define ZYNQ_QSPI_CR_BAUD_MASK		(0x7 << 3)	/* Baud rate
> div */
> -#define ZYNQ_QSPI_CR_CPHA_MASK		(1 << 2)	/* Clock phase */
> -#define ZYNQ_QSPI_CR_CPOL_MASK		(1 << 1)	/* Clock polarity */
> -#define ZYNQ_QSPI_CR_MSTREN_MASK	(1 << 0)	/* Mode select */
> -#define ZYNQ_QSPI_IXR_RXNEMPTY_MASK	(1 << 4)	/*
> RX_FIFO_not_empty */
> -#define ZYNQ_QSPI_IXR_TXOW_MASK		(1 << 2)	/*
> TX_FIFO_not_full */
> +#define ZYNQ_QSPI_CR_CPHA_MASK		BIT(2)	/* Clock
> phase */
> +#define ZYNQ_QSPI_CR_CPOL_MASK		BIT(1)	/* Clock
> polarity */
> +#define ZYNQ_QSPI_CR_MSTREN_MASK	BIT(0)	/* Mode select */
> +#define ZYNQ_QSPI_IXR_RXNEMPTY_MASK	BIT(4)	/*
> RX_FIFO_not_empty */
> +#define ZYNQ_QSPI_IXR_TXOW_MASK		BIT(2)	/*
> TX_FIFO_not_full */
>  #define ZYNQ_QSPI_IXR_ALL_MASK		0x7F		/* All IXR bits
> */
> -#define ZYNQ_QSPI_ENR_SPI_EN_MASK	(1 << 0)	/* SPI Enable */
> +#define ZYNQ_QSPI_ENR_SPI_EN_MASK	BIT(0)	/* SPI Enable */
> 
>  /* zynq qspi Transmit Data Register */
>  #define ZYNQ_QSPI_TXD_00_00_OFFSET	0x1C	/* Transmit 4-byte
> inst */
> diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c index
> 65a9633..92e5712 100644
> --- a/drivers/spi/zynq_spi.c
> +++ b/drivers/spi/zynq_spi.c
> @@ -20,17 +20,17 @@
>  DECLARE_GLOBAL_DATA_PTR;
> 
>  /* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
> -#define ZYNQ_SPI_CR_MSA_MASK		(1 << 15)	/* Manual
> start enb */
> -#define ZYNQ_SPI_CR_MCS_MASK		(1 << 14)	/* Manual
> chip select */
> +#define ZYNQ_SPI_CR_MSA_MASK		BIT(15)	/* Manual start enb
> */
> +#define ZYNQ_SPI_CR_MCS_MASK		BIT(14)	/* Manual chip select
> */
>  #define ZYNQ_SPI_CR_CS_MASK		(0xF << 10)	/* Chip select
> */
>  #define ZYNQ_SPI_CR_BAUD_MASK		(0x7 << 3)	/* Baud rate
> div */
> -#define ZYNQ_SPI_CR_CPHA_MASK		(1 << 2)	/* Clock phase */
> -#define ZYNQ_SPI_CR_CPOL_MASK		(1 << 1)	/* Clock polarity */
> -#define ZYNQ_SPI_CR_MSTREN_MASK		(1 << 0)	/* Mode
> select */
> -#define ZYNQ_SPI_IXR_RXNEMPTY_MASK	(1 << 4)	/*
> RX_FIFO_not_empty */
> -#define ZYNQ_SPI_IXR_TXOW_MASK		(1 << 2)	/* TX_FIFO_not_full
> */
> +#define ZYNQ_SPI_CR_CPHA_MASK		BIT(2)	/* Clock phase */
> +#define ZYNQ_SPI_CR_CPOL_MASK		BIT(1)	/* Clock polarity */
> +#define ZYNQ_SPI_CR_MSTREN_MASK		BIT(0)	/* Mode
> select */
> +#define ZYNQ_SPI_IXR_RXNEMPTY_MASK	BIT(4)	/*
> RX_FIFO_not_empty */
> +#define ZYNQ_SPI_IXR_TXOW_MASK		BIT(2)	/*
> TX_FIFO_not_full */
>  #define ZYNQ_SPI_IXR_ALL_MASK		0x7F		/* All IXR bits
> */
> -#define ZYNQ_SPI_ENR_SPI_EN_MASK	(1 << 0)	/* SPI Enable */
> +#define ZYNQ_SPI_ENR_SPI_EN_MASK	BIT(0)	/* SPI Enable */
> 
>  #define ZYNQ_SPI_CR_BAUD_MAX		8	/* Baud rate divisor
> max val */
>  #define ZYNQ_SPI_CR_BAUD_SHIFT		3	/* Baud rate divisor
> shift */
> --
> 1.9.1