On Monday, October 26, 2015 at 09:36:51 AM, Stefan Roese wrote:
Hi!
[...]
> diff --git a/board/sr1500/socfpga.c b/board/sr1500/socfpga.c
> new file mode 100644
> index 0000000..35d68a9
> --- /dev/null
> +++ b/board/sr1500/socfpga.c
> @@ -0,0 +1,151 @@
> +/*
> + * Copyright (C) 2015 Stefan Roese <sr at denx.de>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <i2c.h>
> +#include <miiphy.h>
> +#include <asm/arch/reset_manager.h>
> +#include <asm/gpio.h>
> +#include <asm/io.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +void s_init(void) {}
> +
> +/*
> + * Miscellaneous platform dependent initialisations
> + */
> +int board_init(void)
> +{
> + /* Address of boot parameters for ATAG (if ATAG is used) */
> + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
> +
> + return 0;
> +}
> +
> +int board_early_init_f(void)
> +{
> + int ret;
> +
> + /* Reset the Marvell PHY 88E1510 */
> + ret = gpio_request(63, "PHY reset");
> + if (ret)
> + return ret;
> +
> + gpio_direction_output(63, 0);
> + mdelay(10);
> + gpio_set_value(63, 1);
> + mdelay(10);
> +
> + return 0;
> +}
> +
> +#define CONFIG_SYS_IDT_CLK_ADDR 0x6a
> +
> +static int do_clksave(cmd_tbl_t *cmdtp, int flag, int argc, char *const
> argv[]) +{
> + u8 buf[1];
u8 buf = 0x1;
i2c_write(....., &buf, 1);
this would work too.
> + buf[0] = 0x01;
> + i2c_write(CONFIG_SYS_IDT_CLK_ADDR, 0, 0, buf, 1);
> +
> + return 0;
> +}
> +
> +U_BOOT_CMD(clksave, 1, 0, do_clksave,
> + "IDT 5V49EE702 Progsave command", "");
Every time you do this in a board file, a kitten dies :-(
[...]
> +static int do_phytest(cmd_tbl_t *cmdtp, int flag, int argc, char *const
> argv[]) +{
> + const char devname[] = NET_DEV_NAME;
> + unsigned long ts;
> + char str[32];
> + u8 addr = 0;
> + u16 data;
> + u16 status;
> + u16 oldpage;
> + int i;
> +
> + /* Save current page register */
> + miiphy_read(devname, addr, MII_MARVELL_PHY_PAGE, &oldpage);
> +
> + /*
> + * Run cable disgnostics
> + */
> + printf("Running cable diagnostic test...");
> + miiphy_write(devname, addr, MII_MARVELL_PHY_PAGE, 7);
> + miiphy_write(devname, addr, 21, PHY_DIAG_START);
> +
> + ts = get_timer(0);
> + do {
> + miiphy_read(devname, addr, 21, &data);
miiphy_read() can also return an error code I think, in which case $data
would be invalid. Right ?
> + if ((data & PHY_DIAG_BUSY) != PHY_DIAG_BUSY)
> + break;
> +
> + mdelay(1);
> + } while (get_timer(ts) < PHY_DIAG_TIMEOUT);
> + printf("done!\n");
> +
> + miiphy_read(devname, addr, 20, &status);
> +
> + for (i = 0; i < 4; i++) {
> + int val;
> +
> + val = (status >> (i * 4)) & 0x000f;
> + pair_state(val, str);
> + printf("Pair %d: %s", i, str);
> +
> + /* Only print fault length if not okay */
> + if (val != 0x01) {
> + miiphy_read(devname, addr, 16 + i, &data);
> + printf(" - Length to fault %d cm", data);
> + }
> + printf("\n");
> + }
> +
> + /* Restore original page */
> + miiphy_write(devname, addr, MII_MARVELL_PHY_PAGE, oldpage);
> +
> + return 0;
> +}
> +
> +U_BOOT_CMD(phytest, 1, 1, do_phytest,
> + "Marvell PHY test command - dump some values", "");
And yet another kitten down ;-)
[...]
> diff --git a/doc/README.socfpga b/doc/README.socfpga
Please , put this README into a separate patch :-(
> index cfcbbfe..eebf373 100644
> --- a/doc/README.socfpga
> +++ b/doc/README.socfpga
> @@ -7,7 +7,6 @@ This README is about U-Boot and SPL support for Altera's
> ARM Cortex-A9MPCore based SOCFPGA. To know more about the hardware itself,
> please refer to www.altera.com.
>
> -
> --------------------------------------------
> socfpga_dw_mmc
> --------------------------------------------
> @@ -51,3 +50,76 @@ the card
> #define CONFIG_SOCFPGA_DWMMC_BUS_HZ 50000000
> -> The clock rate to controller. Do note the controller have a wrapper
> which divide the clock from PLL by 4.
> +
> +-------------------------------------------------------------------------
> +Generating the header files for SPL intergration as a replacement for the
> +Preloader
> +-------------------------------------------------------------------------
> +This text assumes the use of Quartus 14.0.200
> +
> +I) Rebuilding the MCVEVK Quartus project
This is not MCV-specific ;-)
> +----------------------------------------
> + 1) Navigate to DENX_MCV_reference_* directory
> + 2) Run Quartus II
> + 3) Open Project (Ctrl+J), select DENX_MCV_reference.qpf
> + 4) Run QSys [Tools->QSys]
> + 4.1) In the Open dialog, select 'mcv_hps.qsys'
> + 4.2) In the Open System dialog, wait until completion and press
> 'Close' + 4.3) In the Qsys window, click on 'Generate HDL...' in bottom
> right corner + 4.3.1) In the 'Generation' window, click 'Generate'
> + 4.3.2) In the 'Generate' dialog, wait until completion and click
'Close'
> + 4.4) In the QSys window, click 'Finish'
> + 4.4.1) In the 'Quartus II' pop up window, click 'OK'
> + 5) Back in Quartus II main window, do the following
> + 5.1) Use Processing -> Start -> Start Analysis & Synthesis (Ctrl+K)
> + 5.2) Use Processing -> Start Compilation (Ctrl+L)
> + ... have lunch, coffee, play games ...
> +
> + [
> + NOTE: Steps 2-5 above can be also done using a convenience scripts
> + from the command line:
> + $ ./qsys.sh && ./anal.sh && ./build.sh
This is definitelly NOT standard . Please drop this NOTE altogether.
You can use something like the following to compile the quartus project,
which is standard way to do it (that replaces that anal.sh and build.sh
scripts):
$ quartus_sh --flow compile <project>
To generate the qsys system (replacement for qsys.sh), hrm, I guess you
should use "ip-generate", but that takes many options. Dinh, is there some
magic invocation for ip-generate which takes the qsys file and generates
the system ?
> + ]
> +
> + 6) Launch a separate terminal window
> + 6.1) Change directory to 'software/spl_bsp'
> + 6.2) Export path to embedded command shell and friends
> + $ export PATH=/work/DENX/Altera/Quartus/14.0/embedded/:$PATH
14.0 should be replaced by 15.0 ;-)
> + 6.3) Start embedded command shell (ECS)
> + $ embedded_command_shell.sh
> + 6.4) Prepare BSP by launching the BSP editor from ECS
> + => bsp-editor
> + 6.5) In BSP editor
> + 6.5.1) Use File -> Open
> + 6.5.2) Select 'settings.bsp' file
> + 6.5.4) Click Generate
> + 6.5.5) Click Exit
> +
> +Now the necessary files are generated. And U-Boot can be used
> +to generate the SPL header files. For this, please use the
> +following script:
> +
> +./arch/arm/mach-socfpga/qts-filter.sh cyclone5 \
> + /path/to/quartus/project /path/to/output/qts/
> +
> +This will generate the following 4 files:
> +
> +iocsr_config.h
> +pinmux_config.h
> +pll_config.h
> +sdram_config.h
> +
> +These files need to be copied into "qts" directory in the board
> +directory. Here the example for the DENX MCVEVK:
> +
> +$ ll board/denx/mcvevk/qts/
> +total 44
> +drwxrwxr-x 2 stefan stefan 4096 Okt 20 07:07 ./
> +drwxrwxr-x 3 stefan stefan 4096 Okt 21 13:06 ../
> +-rw-rw-r-- 1 stefan stefan 8826 Okt 20 07:07 iocsr_config.h
> +-rw-rw-r-- 1 stefan stefan 4398 Okt 20 07:07 pinmux_config.h
> +-rw-rw-r-- 1 stefan stefan 3192 Okt 20 07:07 pll_config.h
> +-rw-rw-r-- 1 stefan stefan 9031 Okt 20 07:07 sdram_config.h
Oct please ;-)
> +Now you board is ready for full mainline support including
> +U-Boot SPL. The Preloader will not be needed any more.
... is not needed ...
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