[U-Boot] [PATCH V3 12/16] video: mxsfb: introduce lcdif_power_down

[Peng Fan]

Introudce a new function lcdif_power_down.

1. Waits for a VSYNC interrupt to guarantee the reset is done at the
   VSYNC edge, which somehow makes the LCDIF consume the display FIFO(?)
   and helps the LCDIF work normally at the kernel stage.
2. Add power down function to stop lcdif.

The reason to introduce lcdif_power_down is that we want lcdif to be in
initial state when doing uboot reset or before kernel boot to make
system stable, otherwise system may hang.

Signed-off-by: Peng Fan <Peng.Fan at freescale.com>
Cc: Stefano Babic <sbabic at denx.de>
Cc: Anatolij Gustschin <agust at denx.de>
---

V3:
 none
V2:
 none

 arch/arm/include/asm/imx-common/sys_proto.h |  2 ++
 drivers/video/mxsfb.c                       | 17 +++++++++++++++++
 2 files changed, 19 insertions(+)

diff --git a/arch/arm/include/asm/imx-common/sys_proto.h b/arch/arm/include/asm/imx-common/sys_proto.h
index 5673fb4..386c2dc 100644
--- a/arch/arm/include/asm/imx-common/sys_proto.h
+++ b/arch/arm/include/asm/imx-common/sys_proto.h
@@ -47,6 +47,8 @@ int fecmxc_initialize(bd_t *bis);
 u32 get_ahb_clk(void);
 u32 get_periph_clk(void);
 
+void lcdif_power_down(void);
+
 int mxs_reset_block(struct mxs_register_32 *reg);
 int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
 int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index eed57d5..ddbb118 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -131,6 +131,23 @@ static void mxs_lcd_init(GraphicDevice *panel,
 	writel(LCDIF_CTRL_RUN, &regs->hw_lcdif_ctrl_set);
 }
 
+void lcdif_power_down(void)
+{
+	struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
+	int timeout = 1000000;
+
+	writel(panel.frameAdrs, &regs->hw_lcdif_cur_buf_reg);
+	writel(panel.frameAdrs, &regs->hw_lcdif_next_buf_reg);
+	writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, &regs->hw_lcdif_ctrl1_clr);
+	while (--timeout) {
+		if (readl(&regs->hw_lcdif_ctrl1_reg) &
+		    LCDIF_CTRL1_VSYNC_EDGE_IRQ)
+			break;
+		udelay(1);
+	}
+	mxs_reset_block((struct mxs_register_32 *)&regs->hw_lcdif_ctrl_reg);
+}
+
 void *video_hw_init(void)
 {
 	int bpp = -1;
-- 
1.8.4