[U-Boot] [PATCH v0 4/5] arm: mvebu: Fix ddr3_init() cpu config

[Stefan Roese]

Hi Dirk,

On 29.10.2015 10:51, Dirk Eibach wrote:
> 2015-10-28 17:35 GMT+01:00 Stefan Roese <sr at denx.de>:
>> Hi Dirk,
>>
>> On 28.10.2015 16:44, dirk.eibach at gdsys.cc wrote:
>>>
>>> From: Dirk Eibach <dirk.eibach at gdsys.cc>
>>>
>>> Armada 38x has a maximum of two cores. Probably copy/paste
>>> bug from Armada XP.
>>>
>>> Signed-off-by: Dirk Eibach <dirk.eibach at gdsys.cc>
>>> ---
>>>
>>>    drivers/ddr/marvell/a38x/ddr3_init.c | 2 --
>>>    1 file changed, 2 deletions(-)
>>>
>>> diff --git a/drivers/ddr/marvell/a38x/ddr3_init.c
>>> b/drivers/ddr/marvell/a38x/ddr3_init.c
>>> index d6ed8e0..cbfc58c 100644
>>> --- a/drivers/ddr/marvell/a38x/ddr3_init.c
>>> +++ b/drivers/ddr/marvell/a38x/ddr3_init.c
>>> @@ -306,8 +306,6 @@ int ddr3_init(void)
>>>                  SAR1_CPU_CORE_OFFSET;
>>>          switch (soc_num) {
>>>          case 0x3:
>>> -               reg_bit_set(CPU_CONFIGURATION_REG(3), CPU_MRVL_ID_OFFSET);
>>> -               reg_bit_set(CPU_CONFIGURATION_REG(2), CPU_MRVL_ID_OFFSET);
>>>          case 0x1:
>>>                  reg_bit_set(CPU_CONFIGURATION_REG(1), CPU_MRVL_ID_OFFSET);
>>>          case 0x0:
>>
>>
>> Shouldn't you remove the "case 0x3:" line as well?
>
> Nope, according to Reset Configuration Pins table in the hardware spec
> 0 means Armada 380 (singlecore), 1 means Armada 385 (dualcore) and 3
> means Armada 388 (dualcore). So handling soc_num 1 and 3 the same way
> is perfectly allright.

Thanks for the explanation:

Reviewed-by: Stefan Roese <sr at denx.de>

Thanks,
Stefan