[U-Boot] [PATCH v6 09/10] mips: ath79: add AP121 reference board

Wills Wang wills.wang at live.com
Mon Jan 4 12:15:00 CET 2016


Signed-off-by: Wills Wang <wills.wang at live.com>
---

Changes in v6:
- Convert SZ_XXX into hex in ap121.h
- Remove useless CONFIG_SYS_INIT_SP_OFFSET in ap121.h
- Add board_early_init_f for DDR and pin initialization
- Select UART and SPI in ap121_defconfig

Changes in v5:
- Move CONFIG_SYS_TEXT_BASE into ap121.h, and remove config.mk
- Remove useless README file
- Remove useless checkboard function

Changes in v4: None
Changes in v3:
- Add support for device tree

Changes in v2:
- Add a reference board implemention

 arch/mips/dts/Makefile        |  2 +-
 arch/mips/dts/ap121.dts       | 37 ++++++++++++++++++++
 arch/mips/dts/ar933x.dtsi     | 64 ++++++++++++++++++++++++++++++++++
 arch/mips/mach-ath79/Kconfig  | 11 ++++++
 board/ath79/ap121/Kconfig     |  9 +++++
 board/ath79/ap121/MAINTAINERS |  6 ++++
 board/ath79/ap121/Makefile    |  5 +++
 board/ath79/ap121/ap121.c     | 48 +++++++++++++++++++++++++
 configs/ap121_defconfig       | 42 ++++++++++++++++++++++
 include/configs/ap121.h       | 81 +++++++++++++++++++++++++++++++++++++++++++
 10 files changed, 304 insertions(+), 1 deletion(-)
 create mode 100644 arch/mips/dts/ap121.dts
 create mode 100644 arch/mips/dts/ar933x.dtsi
 create mode 100644 board/ath79/ap121/Kconfig
 create mode 100644 board/ath79/ap121/MAINTAINERS
 create mode 100644 board/ath79/ap121/Makefile
 create mode 100644 board/ath79/ap121/ap121.c
 create mode 100644 configs/ap121_defconfig
 create mode 100644 include/configs/ap121.h

diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 47b6eb5..3fd49eb 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-dtb-y +=
+dtb-$(CONFIG_BOARD_AP121) += ap121.dtb
 
 targets += $(dtb-y)
 
diff --git a/arch/mips/dts/ap121.dts b/arch/mips/dts/ap121.dts
new file mode 100644
index 0000000..f7c3a1a
--- /dev/null
+++ b/arch/mips/dts/ap121.dts
@@ -0,0 +1,37 @@
+/dts-v1/;
+#include "ar933x.dtsi"
+
+/ {
+	model = "AP121 Reference Board";
+	compatible = "qca,ap121", "qca,ar933x";
+
+	aliases {
+		spi0 = &spi0;
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&xtal {
+	clock-frequency = <25000000>;
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&spi0 {
+	spi-max-frequency = <25000000>;
+	status = "okay";
+	spi-flash at 0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		memory-map = <0x9f000000 0x00800000>;
+		spi-max-frequency = <25000000>;
+		reg = <0>;
+	};
+};
diff --git a/arch/mips/dts/ar933x.dtsi b/arch/mips/dts/ar933x.dtsi
new file mode 100644
index 0000000..05cc165
--- /dev/null
+++ b/arch/mips/dts/ar933x.dtsi
@@ -0,0 +1,64 @@
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "qca,ar933x";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu at 0 {
+			device_type = "cpu";
+			compatible = "mips,mips24Kc";
+			reg = <0>;
+		};
+	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		xtal: xtal {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-output-names = "xtal";
+		};
+	};
+
+	ahb {
+		compatible = "simple-bus";
+		ranges;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		apb {
+			compatible = "simple-bus";
+			ranges;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			uart0: uart at 18020000 {
+				compatible = "qca,ar9330-uart";
+				reg = <0x18020000 0x20>;
+
+				status = "disabled";
+			};
+		};
+
+		spi0: spi at 1f000000 {
+			compatible = "qca,ar7100-spi";
+			reg = <0x1f000000 0x10>;
+
+			status = "disabled";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig
index f7801e4..0fcd96a 100644
--- a/arch/mips/mach-ath79/Kconfig
+++ b/arch/mips/mach-ath79/Kconfig
@@ -27,4 +27,15 @@ config SOC_QCA953X
 	help
 	  This supports QCA/Atheros qca953x family SOCs.
 
+choice
+	prompt "Board select"
+
+config BOARD_AP121
+	bool "AP121 Reference Board"
+	select SOC_AR933X
+
+endchoice
+
+source "board/ath79/ap121/Kconfig"
+
 endmenu
diff --git a/board/ath79/ap121/Kconfig b/board/ath79/ap121/Kconfig
new file mode 100644
index 0000000..ec72914
--- /dev/null
+++ b/board/ath79/ap121/Kconfig
@@ -0,0 +1,9 @@
+if BOARD_AP121
+
+config SYS_BOARD
+	default "ap121"
+
+config SYS_CONFIG_NAME
+	default "ap121"
+
+endif
diff --git a/board/ath79/ap121/MAINTAINERS b/board/ath79/ap121/MAINTAINERS
new file mode 100644
index 0000000..319b521
--- /dev/null
+++ b/board/ath79/ap121/MAINTAINERS
@@ -0,0 +1,6 @@
+AP121 BOARD
+M:	Wills Wang <wills.wang at live.com>
+S:	Maintained
+F:	board/ath79/ap121/
+F:	include/configs/ap121.h
+F:	configs/ap121_defconfig
diff --git a/board/ath79/ap121/Makefile b/board/ath79/ap121/Makefile
new file mode 100644
index 0000000..ced5432
--- /dev/null
+++ b/board/ath79/ap121/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= ap121.o
diff --git a/board/ath79/ap121/ap121.c b/board/ath79/ap121/ap121.c
new file mode 100644
index 0000000..901b09a
--- /dev/null
+++ b/board/ath79/ap121/ap121.c
@@ -0,0 +1,48 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <wills.wang at live.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/ddr.h>
+#include <debug_uart.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+	void __iomem *regs;
+	u32 val;
+
+	regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
+			   MAP_NOCACHE);
+
+	/*
+	 * GPIO9 as input, GPIO10 as output
+	 */
+	val = readl(regs + AR71XX_GPIO_REG_OE);
+	val &= ~AR933X_GPIO(9);
+	val |= AR933X_GPIO(10);
+	writel(val, regs + AR71XX_GPIO_REG_OE);
+
+	/*
+	 * Enable UART, GPIO9 as UART_SI, GPIO10 as UART_SO
+	 */
+	val = readl(regs + AR71XX_GPIO_REG_FUNC);
+	val |= AR933X_GPIO_FUNC_UART_EN | AR933X_GPIO_FUNC_RES_TRUE;
+	writel(val, regs + AR71XX_GPIO_REG_FUNC);
+
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
+	ddr_init();
+	return 0;
+}
+#endif
diff --git a/configs/ap121_defconfig b/configs/ap121_defconfig
new file mode 100644
index 0000000..d928ba8
--- /dev/null
+++ b/configs/ap121_defconfig
@@ -0,0 +1,42 @@
+CONFIG_MIPS=y
+CONFIG_ARCH_ATH79=y
+CONFIG_BOARD_AP121=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_AR933X_UART=y
+CONFIG_DM_SERIAL=y
+CONFIG_ATH79_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="ap121"
+CONFIG_SYS_PROMPT="ap121 # "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_AR933X=y
+CONFIG_DEBUG_UART_BASE=0x18020000
+CONFIG_DEBUG_UART_CLOCK=25000000
diff --git a/include/configs/ap121.h b/include/configs/ap121.h
new file mode 100644
index 0000000..04a80e7
--- /dev/null
+++ b/include/configs/ap121.h
@@ -0,0 +1,81 @@
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_TEXT_BASE            0x9f000000
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SYS_HZ                   1000
+#define CONFIG_SYS_MHZ                  200
+#define CONFIG_SYS_MIPS_TIMER_FREQ      (CONFIG_SYS_MHZ * 1000000)
+
+/* Cache Configuration */
+#define CONFIG_SYS_DCACHE_SIZE          0x8000
+#define CONFIG_SYS_ICACHE_SIZE          0x10000
+#define CONFIG_SYS_CACHELINE_SIZE       32
+
+#define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_MALLOC_LEN           0x40000
+#define CONFIG_SYS_BOOTPARAMS_LEN       0x20000
+
+#define CONFIG_SYS_SDRAM_BASE           0x80000000
+#define CONFIG_SYS_LOAD_ADDR            0x81000000
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SYS_INIT_RAM_ADDR        0xbd000000
+#define CONFIG_SYS_INIT_RAM_SIZE        0x8000
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1)
+
+#define CONFIG_BAUDRATE                 115200
+#define CONFIG_SYS_BAUDRATE_TABLE \
+	{9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_BOOTDELAY                3
+#define CONFIG_BOOTARGS                 "console=ttyS0,115200 " \
+					"root=/dev/mtdblock2 " \
+					"rootfstype=squashfs"
+#define CONFIG_BOOTCOMMAND              "sf probe;" \
+					"mtdparts default;" \
+					"bootm 0x9f300000"
+#define CONFIG_LZMA
+#define CONFIG_OF_LIBFDT
+
+#define MTDIDS_DEFAULT                  "nor0=spi-flash.0"
+#define MTDPARTS_DEFAULT                "mtdparts=spi-flash.0:" \
+					"256k(u-boot),64k(u-boot-env)," \
+					"2752k(rootfs),896k(uImage)," \
+					"64k(NVRAM),64k(ART)"
+
+#define CONFIG_ENV_SPI_MAX_HZ           25000000
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET               0x40000
+#define CONFIG_ENV_SECT_SIZE            0x10000
+#define CONFIG_ENV_SIZE                 0x10000
+
+/*
+ * Command
+ */
+#define CONFIG_CMD_MTDPARTS
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_CBSIZE               256
+#define CONFIG_SYS_MAXARGS              16
+#define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_MEMTEST_START        0x80100000
+#define CONFIG_SYS_MEMTEST_END          0x83f00000
+#define CONFIG_CMD_MEMTEST
+
+#endif  /* __CONFIG_H */
-- 
1.9.1



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