[U-Boot] [PATCH v7 7/7] mips: ath79: add AP143 reference board
Daniel Schwierzeck
daniel.schwierzeck at gmail.com
Sat Jan 16 20:53:09 CET 2016
Am Sonntag, den 17.01.2016, 02:13 +0800 schrieb Wills Wang:
> Signed-off-by: Wills Wang <wills.wang at live.com>
my comments in patch 6/7 apply to this patch too
> ---
>
> Changes in v7:
> - Use KSEG1 address for debug port in ap143
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
> arch/mips/dts/Makefile | 1 +
> arch/mips/dts/ap143.dts | 43 ++++++++++++++++++++
> arch/mips/dts/qca953x.dtsi | 72
> ++++++++++++++++++++++++++++++++++
> arch/mips/mach-ath79/Kconfig | 5 +++
> board/ath79/ap143/Kconfig | 9 +++++
> board/ath79/ap143/MAINTAINERS | 6 +++
> board/ath79/ap143/Makefile | 5 +++
> board/ath79/ap143/ap143.c | 63 ++++++++++++++++++++++++++++++
> configs/ap143_defconfig | 43 ++++++++++++++++++++
> include/configs/ap143.h | 91
> +++++++++++++++++++++++++++++++++++++++++++
> 10 files changed, 338 insertions(+)
> create mode 100644 arch/mips/dts/ap143.dts
> create mode 100644 arch/mips/dts/qca953x.dtsi
> create mode 100644 board/ath79/ap143/Kconfig
> create mode 100644 board/ath79/ap143/MAINTAINERS
> create mode 100644 board/ath79/ap143/Makefile
> create mode 100644 board/ath79/ap143/ap143.c
> create mode 100644 configs/ap143_defconfig
> create mode 100644 include/configs/ap143.h
>
> diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
> index 3fd49eb..7da06c5 100644
> --- a/arch/mips/dts/Makefile
> +++ b/arch/mips/dts/Makefile
> @@ -3,6 +3,7 @@
> #
>
> dtb-$(CONFIG_BOARD_AP121) += ap121.dtb
> +dtb-$(CONFIG_BOARD_AP143) += ap143.dtb
>
> targets += $(dtb-y)
>
> diff --git a/arch/mips/dts/ap143.dts b/arch/mips/dts/ap143.dts
> new file mode 100644
> index 0000000..f53207e
> --- /dev/null
> +++ b/arch/mips/dts/ap143.dts
> @@ -0,0 +1,43 @@
> +/*
> + * Copyright (C) 2015-2016 Wills Wang <wills.wang at live.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +/dts-v1/;
> +#include "qca953x.dtsi"
> +
> +/ {
> + model = "AP143 Reference Board";
> + compatible = "qca,ap143", "qca,qca953x";
> +
> + aliases {
> + spi0 = &spi0;
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> +&xtal {
> + clock-frequency = <25000000>;
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> +
> +&spi0 {
> + spi-max-frequency = <25000000>;
> + status = "okay";
> + spi-flash at 0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "spi-flash";
> + memory-map = <0x9f000000 0x00800000>;
> + spi-max-frequency = <25000000>;
> + reg = <0>;
> + };
> +};
> diff --git a/arch/mips/dts/qca953x.dtsi b/arch/mips/dts/qca953x.dtsi
> new file mode 100644
> index 0000000..8487fc9
> --- /dev/null
> +++ b/arch/mips/dts/qca953x.dtsi
> @@ -0,0 +1,72 @@
> +/*
> + * Copyright (C) 2015-2016 Wills Wang <wills.wang at live.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include "skeleton.dtsi"
> +
> +/ {
> + compatible = "qca,qca953x";
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu at 0 {
> + device_type = "cpu";
> + compatible = "mips,mips24Kc";
> + reg = <0>;
> + };
> + };
> +
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + xtal: xtal {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-output-names = "xtal";
> + };
> + };
> +
> + ahb {
> + compatible = "simple-bus";
> + ranges;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + apb {
> + compatible = "simple-bus";
> + ranges;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + uart0: uart at 18020000 {
> + compatible = "ns16550";
> + reg = <0x18020000 0x20>;
> + reg-shift = <2>;
> + clock-frequency = <25000000>;
> +
> + status = "disabled";
> + };
> + };
> +
> + spi0: spi at 1f000000 {
> + compatible = "qca,ar7100-spi";
> + reg = <0x1f000000 0x10>;
> +
> + status = "disabled";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +};
> diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach
> -ath79/Kconfig
> index 0fcd96a..f61efd2 100644
> --- a/arch/mips/mach-ath79/Kconfig
> +++ b/arch/mips/mach-ath79/Kconfig
> @@ -34,8 +34,13 @@ config BOARD_AP121
> bool "AP121 Reference Board"
> select SOC_AR933X
>
> +config BOARD_AP143
> + bool "AP143 Reference Board"
> + select SOC_QCA953X
> +
> endchoice
>
> source "board/ath79/ap121/Kconfig"
> +source "board/ath79/ap143/Kconfig"
>
> endmenu
> diff --git a/board/ath79/ap143/Kconfig b/board/ath79/ap143/Kconfig
> new file mode 100644
> index 0000000..118b9b5
> --- /dev/null
> +++ b/board/ath79/ap143/Kconfig
> @@ -0,0 +1,9 @@
> +if BOARD_AP143
> +
> +config SYS_BOARD
> + default "ap143"
> +
> +config SYS_CONFIG_NAME
> + default "ap143"
> +
> +endif
> diff --git a/board/ath79/ap143/MAINTAINERS
> b/board/ath79/ap143/MAINTAINERS
> new file mode 100644
> index 0000000..d373cf8
> --- /dev/null
> +++ b/board/ath79/ap143/MAINTAINERS
> @@ -0,0 +1,6 @@
> +AP143 BOARD
> +M: Wills Wang <wills.wang at live.com>
> +S: Maintained
> +F: board/ath79/ap143/
> +F: include/configs/ap143.h
> +F: configs/ap143_defconfig
> diff --git a/board/ath79/ap143/Makefile b/board/ath79/ap143/Makefile
> new file mode 100644
> index 0000000..00f7837
> --- /dev/null
> +++ b/board/ath79/ap143/Makefile
> @@ -0,0 +1,5 @@
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +obj-y = ap143.o
> diff --git a/board/ath79/ap143/ap143.c b/board/ath79/ap143/ap143.c
> new file mode 100644
> index 0000000..3be86e6
> --- /dev/null
> +++ b/board/ath79/ap143/ap143.c
> @@ -0,0 +1,63 @@
> +/*
> + * Copyright (C) 2015-2016 Wills Wang <wills.wang at live.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/addrspace.h>
> +#include <asm/types.h>
> +#include <mach/ar71xx_regs.h>
> +#include <mach/ddr.h>
> +#include <debug_uart.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#ifdef CONFIG_BOARD_EARLY_INIT_F
> +int board_early_init_f(void)
> +{
> + void __iomem *regs;
> + u32 val;
> +
> + regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
> + MAP_NOCACHE);
> +
> + /*
> + * GPIO9 as input, GPIO10 as output
> + */
> + val = readl(regs + AR71XX_GPIO_REG_OE);
> + val |= QCA953X_GPIO(9);
> + val &= ~QCA953X_GPIO(10);
> + writel(val, regs + AR71XX_GPIO_REG_OE);
> +
> + /*
> + * Enable GPIO10 as UART0_SOUT
> + */
> + val = readl(regs + QCA953X_GPIO_REG_OUT_FUNC2);
> + val &= ~QCA953X_GPIO_OUT_MUX_MASK(16);
> + val |= QCA953X_GPIO_OUT_MUX_UART0_SOUT << 16;
> + writel(val, regs + QCA953X_GPIO_REG_OUT_FUNC2);
> +
> + /*
> + * Enable GPIO9 as UART0_SIN
> + */
> + val = readl(regs + QCA953X_GPIO_REG_IN_ENABLE0);
> + val &= ~QCA953X_GPIO_OUT_MUX_MASK(8);
> + val |= QCA953X_GPIO_IN_MUX_UART0_SIN << 8;
> + writel(val, regs + QCA953X_GPIO_REG_IN_ENABLE0);
> +
> + /*
> + * Enable GPIO10 output
> + */
> + val = readl(regs + AR71XX_GPIO_REG_OUT);
> + val |= QCA953X_GPIO(10);
> + writel(val, regs + AR71XX_GPIO_REG_OUT);
> +
> +#ifdef CONFIG_DEBUG_UART
> + debug_uart_init();
> +#endif
> + ddr_init();
> + return 0;
> +}
> +#endif
> diff --git a/configs/ap143_defconfig b/configs/ap143_defconfig
> new file mode 100644
> index 0000000..ed7e09d
> --- /dev/null
> +++ b/configs/ap143_defconfig
> @@ -0,0 +1,43 @@
> +CONFIG_MIPS=y
> +CONFIG_ARCH_ATH79=y
> +CONFIG_BOARD_AP143=y
> +CONFIG_SYS_MALLOC_F_LEN=0x800
> +CONFIG_SYS_NS16550=y
> +CONFIG_DM_SERIAL=y
> +CONFIG_ATH79_SPI=y
> +CONFIG_DM_SPI=y
> +CONFIG_DM_SPI_FLASH=y
> +CONFIG_DEFAULT_DEVICE_TREE="ap143"
> +CONFIG_SYS_PROMPT="ap143 # "
> +# CONFIG_CMD_BDI is not set
> +# CONFIG_CMD_CONSOLE is not set
> +# CONFIG_CMD_ELF is not set
> +# CONFIG_CMD_IMLS is not set
> +# CONFIG_CMD_XIMG is not set
> +# CONFIG_CMD_EXPORTENV is not set
> +# CONFIG_CMD_IMPORTENV is not set
> +# CONFIG_CMD_EDITENV is not set
> +# CONFIG_CMD_CRC32 is not set
> +# CONFIG_CMD_FLASH is not set
> +CONFIG_CMD_SF=y
> +CONFIG_CMD_SPI=y
> +# CONFIG_CMD_FPGA is not set
> +# CONFIG_CMD_NET is not set
> +# CONFIG_CMD_NFS is not set
> +CONFIG_SPI_FLASH=y
> +CONFIG_SPI_FLASH_BAR=y
> +CONFIG_SPI_FLASH_ATMEL=y
> +CONFIG_SPI_FLASH_EON=y
> +CONFIG_SPI_FLASH_GIGADEVICE=y
> +CONFIG_SPI_FLASH_MACRONIX=y
> +CONFIG_SPI_FLASH_SPANSION=y
> +CONFIG_SPI_FLASH_STMICRO=y
> +CONFIG_SPI_FLASH_SST=y
> +CONFIG_SPI_FLASH_WINBOND=y
> +CONFIG_SPI_FLASH_DATAFLASH=y
> +CONFIG_SPI_FLASH_MTD=y
> +CONFIG_DEBUG_UART=y
> +CONFIG_DEBUG_UART_NS16550=y
> +CONFIG_DEBUG_UART_BASE=0xb8020000
> +CONFIG_DEBUG_UART_CLOCK=25000000
> +CONFIG_DEBUG_UART_SHIFT=2
> diff --git a/include/configs/ap143.h b/include/configs/ap143.h
> new file mode 100644
> index 0000000..6940551
> --- /dev/null
> +++ b/include/configs/ap143.h
> @@ -0,0 +1,91 @@
> +/*
> + * Copyright (C) 2015-2016 Wills Wang <wills.wang at live.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#define CONFIG_SYS_TEXT_BASE 0x9f000000
> +
> +#define CONFIG_DISPLAY_CPUINFO
> +#define CONFIG_DISPLAY_BOARDINFO
> +#define CONFIG_BOARD_EARLY_INIT_F
> +
> +#define CONFIG_SYS_HZ 1000
> +#define CONFIG_SYS_MHZ 325
> +#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
> +
> +/* Cache Configuration */
> +#define CONFIG_SYS_DCACHE_SIZE 0x8000
> +#define CONFIG_SYS_ICACHE_SIZE 0x10000
> +#define CONFIG_SYS_CACHELINE_SIZE 32
> +
> +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
> +
> +#define CONFIG_SYS_MALLOC_LEN 0x40000
> +#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000
> +
> +#define CONFIG_SYS_SDRAM_BASE 0x80000000
> +#define CONFIG_SYS_LOAD_ADDR 0x81000000
> +
> +#define CONFIG_SYS_NO_FLASH
> +
> +#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
> +#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
> +#define CONFIG_SYS_INIT_SP_ADDR \
> + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1)
> +
> +/*
> + * Serial Port
> + */
> +#define CONFIG_SYS_NS16550_CLK 25000000
> +#define CONFIG_BAUDRATE 115200
> +#define CONFIG_SYS_BAUDRATE_TABLE \
> + {9600, 19200, 38400, 57600, 115200}
> +
> +#define CONFIG_BOOTDELAY 3
> +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
> + "root=/dev/mtdblock2 " \
> + "rootfstype=squashfs"
> +#define CONFIG_BOOTCOMMAND "sf probe;" \
> + "mtdparts default;" \
> + "bootm 0x9f300000"
> +#define CONFIG_LZMA
> +#define CONFIG_OF_LIBFDT
> +
> +#define MTDIDS_DEFAULT "nor0=spi-flash.0"
> +#define MTDPARTS_DEFAULT "mtdparts=spi-flash.0:" \
> + "256k(u-boot),64k(u-boot
> -env)," \
> + "2752k(rootfs),896k(uImage),
> " \
> + "64k(NVRAM),64k(ART)"
> +
> +#define CONFIG_ENV_SPI_MAX_HZ 25000000
> +#define CONFIG_ENV_IS_IN_SPI_FLASH
> +#define CONFIG_ENV_OFFSET 0x40000
> +#define CONFIG_ENV_SECT_SIZE 0x10000
> +#define CONFIG_ENV_SIZE 0x10000
> +
> +/*
> + * Command
> + */
> +#define CONFIG_CMD_MTDPARTS
> +
> +/* Miscellaneous configurable options */
> +#define CONFIG_SYS_CBSIZE 256
> +#define CONFIG_SYS_MAXARGS 16
> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
> + sizeof(CONFIG_SYS_PROMPT) +
> 16)
> +#define CONFIG_SYS_LONGHELP
> +#define CONFIG_CMDLINE_EDITING
> +#define CONFIG_AUTO_COMPLETE
> +
> +/*
> + * Diagnostics
> + */
> +#define CONFIG_SYS_MEMTEST_START 0x80100000
> +#define CONFIG_SYS_MEMTEST_END 0x83f00000
> +#define CONFIG_CMD_MEMTEST
> +
> +#endif /* __CONFIG_H */
--
- Daniel
More information about the U-Boot
mailing list