[U-Boot] [PATCH 2/2] arm: mvebu: Add support for the Armada XP theadorable board

Stefan Roese sr at denx.de
Wed Jan 20 08:13:29 CET 2016


This patch adds support for the Armada XP (MV78260) based theadorable
board. Its equipped with onboard DDR3, UART, ethernet, I2C, SPI NOR,
LCD and SATA (SSD) interfaces / devices.

Two defconfigs are added:

theadorable_defconfig:
The production U-Boot version with a stripped down drivers and feature
list. This removes networking, USB and PCI support.

theadorable_debug_defconfig:
The debugging / testing U-Boot version with full support for all drivers.

Signed-off-by: Stefan Roese <sr at denx.de>
Cc: Luka Perkov <luka.perkov at sartura.hr>
---
 arch/arm/dts/Makefile                  |   3 +-
 arch/arm/dts/armada-xp-theadorable.dts | 143 +++++++++++++++++++++++++++
 arch/arm/mach-mvebu/Kconfig            |   6 ++
 board/theadorable/MAINTAINERS          |   7 ++
 board/theadorable/Makefile             |   7 ++
 board/theadorable/kwbimage.cfg         |  12 +++
 board/theadorable/theadorable.c        | 171 +++++++++++++++++++++++++++++++++
 configs/theadorable_debug_defconfig    |  28 ++++++
 configs/theadorable_defconfig          |  26 +++++
 include/configs/theadorable.h          | 170 ++++++++++++++++++++++++++++++++
 10 files changed, 572 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/armada-xp-theadorable.dts
 create mode 100644 board/theadorable/MAINTAINERS
 create mode 100644 board/theadorable/Makefile
 create mode 100644 board/theadorable/kwbimage.cfg
 create mode 100644 board/theadorable/theadorable.c
 create mode 100644 configs/theadorable_debug_defconfig
 create mode 100644 configs/theadorable_defconfig
 create mode 100644 include/configs/theadorable.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e4f8aae..9b933ac 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -52,7 +52,8 @@ dtb-$(CONFIG_ARCH_MVEBU) +=			\
 	armada-388-gp.dtb			\
 	armada-xp-gp.dtb			\
 	armada-xp-maxbcm.dtb			\
-	armada-xp-synology-ds414.dtb
+	armada-xp-synology-ds414.dtb		\
+	armada-xp-theadorable.dtb
 
 dtb-$(CONFIG_ARCH_UNIPHIER) += \
 	uniphier-ph1-ld4-ref.dtb \
diff --git a/arch/arm/dts/armada-xp-theadorable.dts b/arch/arm/dts/armada-xp-theadorable.dts
new file mode 100644
index 0000000..cf1be2a
--- /dev/null
+++ b/arch/arm/dts/armada-xp-theadorable.dts
@@ -0,0 +1,143 @@
+/*
+ * Device Tree file for Marvell Armada XP theadorable board
+ *
+ * Copyright (C) 2013-2014 Marvell
+ *
+ * Lior Amsalem <alior at marvell.com>
+ * Gregory CLEMENT <gregory.clement at free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Note: this Device Tree assumes that the bootloader has remapped the
+ * internal registers to 0xf1000000 (instead of the default
+ * 0xd0000000). The 0xf1000000 is the default used by the recent,
+ * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
+ * boards were delivered with an older version of the bootloader that
+ * left internal registers mapped at 0xd0000000. If you are in this
+ * situation, you should either update your bootloader (preferred
+ * solution) or the below Device Tree should be adjusted.
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "armada-xp-mv78260.dtsi"
+
+/ {
+	model = "Marvell Armada XP theadorable";
+	compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		spi0 = &spi0;
+		ethernet0 = &eth0;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x00000000 0x00000000 0x80000000>;
+	};
+
+	soc {
+		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
+			  MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
+			  MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
+
+		internal-regs {
+			serial at 12000 {
+				status = "okay";
+				u-boot,dm-pre-reloc;
+			};
+
+			serial at 12100 {
+				status = "okay";
+			};
+
+			serial at 12200 {
+				status = "okay";
+			};
+
+			serial at 12300 {
+				status = "okay";
+			};
+
+			sata at a0000 {
+				nr-ports = <2>;
+				status = "okay";
+			};
+
+			mdio {
+				phy0: ethernet-phy at 0 {
+					reg = <0>;
+				};
+			};
+
+			ethernet at 70000 {
+				status = "okay";
+				phy = <&phy0>;
+				phy-mode = "sgmii";
+			};
+
+			usb at 50000 {
+				status = "okay";
+			};
+
+			usb at 51000 {
+				status = "okay";
+			};
+
+			spi0: spi at 10600 {
+				status = "okay";
+				u-boot,dm-pre-reloc;
+
+				spi-flash at 0 {
+					u-boot,dm-pre-reloc;
+					#address-cells = <1>;
+					#size-cells = <1>;
+					compatible = "n25q128a13", "jedec,spi-nor";
+					reg = <0>; /* Chip select 0 */
+					spi-max-frequency = <27777777>;
+				};
+			};
+		};
+	};
+};
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index b962846..96a3313 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -46,6 +46,10 @@ config TARGET_MAXBCM
 	bool "Support maxbcm"
 	select MV78460
 
+config TARGET_THEADORABLE
+	bool "Support theadorable Armada XP"
+	select MV78260
+
 endchoice
 
 config SYS_BOARD
@@ -54,6 +58,7 @@ config SYS_BOARD
 	default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
 	default "ds414" if TARGET_DS414
 	default "maxbcm" if TARGET_MAXBCM
+	default "theadorable" if TARGET_THEADORABLE
 
 config SYS_CONFIG_NAME
 	default "clearfog" if TARGET_CLEARFOG
@@ -61,6 +66,7 @@ config SYS_CONFIG_NAME
 	default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
 	default "ds414" if TARGET_DS414
 	default "maxbcm" if TARGET_MAXBCM
+	default "theadorable" if TARGET_THEADORABLE
 
 config SYS_VENDOR
 	default "Marvell" if TARGET_DB_MV784MP_GP
diff --git a/board/theadorable/MAINTAINERS b/board/theadorable/MAINTAINERS
new file mode 100644
index 0000000..5ae6b64
--- /dev/null
+++ b/board/theadorable/MAINTAINERS
@@ -0,0 +1,7 @@
+THEADORABLE BOARD
+M:	Stefan Roese <sr at denx.de>
+S:	Maintained
+F:	board/theadorable/
+F:	include/configs/theadorable.h
+F:	configs/theadorable_debug_defconfig
+F:	configs/theadorable_defconfig
diff --git a/board/theadorable/Makefile b/board/theadorable/Makefile
new file mode 100644
index 0000000..9d5b39e
--- /dev/null
+++ b/board/theadorable/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015-2016 Stefan Roese <sr at denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= theadorable.o
diff --git a/board/theadorable/kwbimage.cfg b/board/theadorable/kwbimage.cfg
new file mode 100644
index 0000000..4f3b7b2
--- /dev/null
+++ b/board/theadorable/kwbimage.cfg
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2015-2016 Stefan Roese <sr at denx.de>
+#
+
+# Armada XP uses version 1 image format
+VERSION		1
+
+# Boot Media configurations
+BOOT_FROM	spi
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c
new file mode 100644
index 0000000..0e23265
--- /dev/null
+++ b/board/theadorable/theadorable.c
@@ -0,0 +1,171 @@
+/*
+ * Copyright (C) 2015-2016 Stefan Roese <sr at denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#ifdef CONFIG_NET
+#include <netdev.h>
+#endif
+
+#include "../drivers/ddr/marvell/axp/ddr3_hw_training.h"
+#include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define THEADORABLE_GPP_OUT_ENA_LOW	0x00336780
+#define THEADORABLE_GPP_OUT_ENA_MID	0x00003cf0
+#define THEADORABLE_GPP_OUT_ENA_HIGH	(~(0x0))
+
+#define THEADORABLE_GPP_OUT_VAL_LOW	0x2c0c983f
+#define THEADORABLE_GPP_OUT_VAL_MID	0x0007000c
+#define THEADORABLE_GPP_OUT_VAL_HIGH	0x00000000
+
+/* DDR3 static configuration */
+static MV_DRAM_MC_INIT ddr3_theadorable[MV_MAX_DDR3_STATIC_SIZE] = {
+	{0x00001400, 0x7301ca28},	/* DDR SDRAM Configuration Register */
+	{0x00001404, 0x30000800},	/* Dunit Control Low Register */
+	{0x00001408, 0x44149887},	/* DDR SDRAM Timing (Low) Register */
+	{0x0000140C, 0x38d93fc7},	/* DDR SDRAM Timing (High) Register */
+	{0x00001410, 0x1b100001},	/* DDR SDRAM Address Control Register */
+	{0x00001424, 0x0000f3ff},	/* Dunit Control High Register */
+	{0x00001428, 0x000f8830},	/* ODT Timing (Low) Register */
+	{0x0000142C, 0x014c50f4},	/* DDR3 Timing Register */
+	{0x0000147C, 0x0000c671},	/* ODT Timing (High) Register */
+
+	{0x00001494, 0x00010000},	/* DDR SDRAM ODT Control (Low) Reg */
+	{0x0000149C, 0x00000001},	/* DDR Dunit ODT Control Register */
+	{0x000014A0, 0x00000001},	/* DRAM FIFO Control Register */
+	{0x000014A8, 0x00000101},	/* AXI Control Register */
+
+	/*
+	 * DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the
+	 * training sequence
+	 */
+	{0x000200e8, 0x3fff0e01},
+	{0x00020184, 0x3fffffe0},	/* Close fast path Window to - 2G */
+
+	{0x0001504, 0x7fffffe1},	/* CS0 Size */
+	{0x000150C, 0x00000000},	/* CS1 Size */
+	{0x0001514, 0x00000000},	/* CS2 Size */
+	{0x000151C, 0x00000000},	/* CS3 Size */
+
+	{0x00020220, 0x00000007},	/* Reserved */
+
+	{0x00001538, 0x00000009},	/* Read Data Sample Delays Register */
+	{0x0000153C, 0x00000009},	/* Read Data Ready Delay Register */
+
+	{0x000015D0, 0x00000650},	/* MR0 */
+	{0x000015D4, 0x00000044},	/* MR1 */
+	{0x000015D8, 0x00000010},	/* MR2 */
+	{0x000015DC, 0x00000000},	/* MR3 */
+	{0x000015E0, 0x00000001},
+	{0x000015E4, 0x00203c18},	/* ZQDS Configuration Register */
+	{0x000015EC, 0xf800a225},	/* DDR PHY */
+
+	/* Recommended Settings from Marvell for 4 x 16 bit devices: */
+	{0x000014C0, 0x192424c9},	/* DRAM addr and Ctrl Driving Strenght*/
+	{0x000014C4, 0x0aaa24c9},	/* DRAM Data and DQS Driving Strenght */
+
+	{0x0, 0x0}
+};
+
+static MV_DRAM_MODES board_ddr_modes[MV_DDR3_MODES_NUMBER] = {
+	{"theadorable_1333-667", 0x3, 0x5, 0x0, A0, ddr3_theadorable,  NULL},
+};
+
+extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[];
+
+/*
+ * Lane0 - PCIE0.0 X1 (to WIFI Module)
+ * Lane5 - SATA0
+ * Lane6 - SATA1
+ * Lane7 - SGMII0 (to Ethernet Phy)
+ * Lane8-11 - PCIE2.0 X4 (to PEX Switch)
+ * all other lanes are disabled
+ */
+MV_BIN_SERDES_CFG theadorable_serdes_cfg[] = {
+	{ MV_PEX_ROOT_COMPLEX, 0x22200001, 0x00001111,
+	  { PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4,
+	    PEX_BUS_DISABLED },
+	  0x0060, serdes_change_m_phy
+	},
+};
+
+MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
+{
+	/* Only one mode supported for this board */
+	return &board_ddr_modes[0];
+}
+
+MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
+{
+	return &theadorable_serdes_cfg[0];
+}
+
+int board_early_init_f(void)
+{
+	/* Configure MPP */
+	writel(0x00000000, MVEBU_MPP_BASE + 0x00);
+	writel(0x03300000, MVEBU_MPP_BASE + 0x04);
+	writel(0x00000033, MVEBU_MPP_BASE + 0x08);
+	writel(0x00000000, MVEBU_MPP_BASE + 0x0c);
+	writel(0x11110000, MVEBU_MPP_BASE + 0x10);
+	writel(0x00221100, MVEBU_MPP_BASE + 0x14);
+	writel(0x00000000, MVEBU_MPP_BASE + 0x18);
+	writel(0x00000000, MVEBU_MPP_BASE + 0x1c);
+	writel(0x00000000, MVEBU_MPP_BASE + 0x20);
+
+	/* Configure GPIO */
+	writel(THEADORABLE_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+	writel(THEADORABLE_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+	writel(THEADORABLE_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+	writel(THEADORABLE_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+	writel(THEADORABLE_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
+	writel(THEADORABLE_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: theadorable\n");
+
+	return 0;
+}
+
+#ifdef CONFIG_NET
+int board_eth_init(bd_t *bis)
+{
+	cpu_eth_init(bis); /* Built in controller(s) come first */
+	return pci_eth_init(bis);
+}
+#endif
+
+int board_video_init(void)
+{
+	struct mvebu_lcd_info lcd_info;
+
+	/* Reserved memory area via CONFIG_SYS_MEM_TOP_HIDE */
+	lcd_info.fb_base	= gd->ram_size;
+	lcd_info.x_res		= 240;
+	lcd_info.x_fp		= 1;
+	lcd_info.x_bp		= 45;
+	lcd_info.y_res		= 320;
+	lcd_info.y_fp		= 1;
+	lcd_info.y_bp		= 3;
+
+	return mvebu_lcd_register_init(&lcd_info);
+}
diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig
new file mode 100644
index 0000000..fbed23c
--- /dev/null
+++ b/configs/theadorable_debug_defconfig
@@ -0,0 +1,28 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_THEADORABLE=y
+CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xd0012000
+CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_VIDEO_MVEBU=y
diff --git a/configs/theadorable_defconfig b/configs/theadorable_defconfig
new file mode 100644
index 0000000..cce4669
--- /dev/null
+++ b/configs/theadorable_defconfig
@@ -0,0 +1,26 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_THEADORABLE=y
+CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xd0012000
+CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_VIDEO_MVEBU=y
+CONFIG_REGEX=y
+CONFIG_LIB_RAND=y
diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h
new file mode 100644
index 0000000..cd9d6b6
--- /dev/null
+++ b/include/configs/theadorable.h
@@ -0,0 +1,170 @@
+/*
+ * Copyright (C) 2015-2016 Stefan Roese <sr at denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_THEADORABLE_H
+#define _CONFIG_THEADORABLE_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/*
+ * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
+ * for DDR ECC byte filling in the SPL before loading the main
+ * U-Boot into it.
+ */
+#define	CONFIG_SYS_TEXT_BASE	0x00800000
+#define CONFIG_SYS_TCLK		250000000	/* 250MHz */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_SATA
+#define CONFIG_CMD_TIME
+
+/*
+ * The debugging version enables USB support via defconfig.
+ * This version should also enable all other non-production
+ * interfaces / features.
+ */
+#ifdef CONFIG_USB
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_TFTPPUT
+#endif
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MVTWSI
+#define CONFIG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE
+#define CONFIG_SYS_I2C_SLAVE		0x0
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* USB/EHCI configuration */
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
+
+#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
+
+/* SPI NOR flash default params, used by sf commands */
+#define CONFIG_SF_DEFAULT_SPEED		27777777 /* for fast SPL booting */
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET		(1 << 20) /* 1MiB in */
+#define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE		(256 << 10) /* 256KiB sectors */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_PHY_MARVELL		/* there is a marvell phy */
+#define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup */
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_PREBOOT
+#define CONFIG_FIT
+
+#define CONFIG_SYS_HUSH_PARSER			/* Use the HUSH parser	*/
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+/* Keep device tree and initrd in lower memory so the kernel can access them */
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"fdt_high=0x10000000\0"		\
+	"initrd_high=0x10000000\0"
+
+/* SATA support */
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_SATA_MV
+#define CONFIG_LIBATA
+#define CONFIG_LBA48
+#define CONFIG_EFI_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* Additional FS support/configuration */
+#define CONFIG_SUPPORT_VFAT
+
+/* PCIe support */
+#ifdef CONFIG_CMD_PCI
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_PCI
+#define CONFIG_PCI_MVEBU
+#define CONFIG_PCI_PNP
+#endif
+#endif
+
+/* Enable LCD and reserve 512KB from top of memory*/
+#define CONFIG_SYS_MEM_TOP_HIDE		0x80000
+
+#define CONFIG_VIDEO
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_CMD_BMP
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ * Memory layout while starting into the bin_hdr via the
+ * BootROM:
+ *
+ * 0x4000.4000 - 0x4003.4000	headers space (192KiB)
+ * 0x4000.4030			bin_hdr start address
+ * 0x4003.4000 - 0x4004.7c00	BootROM memory allocations (15KiB)
+ * 0x4007.fffc			BootROM stack top
+ *
+ * The address space between 0x4007.fffc and 0x400f.fff is not locked in
+ * L2 cache thus cannot be used.
+ */
+
+/* SPL */
+/* Defines for SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE		0x40004030
+#define CONFIG_SPL_MAX_SIZE		((128 << 10) - 0x4030)
+
+#define CONFIG_SPL_BSS_START_ADDR	(0x40000000 + (128 << 10))
+#define CONFIG_SPL_BSS_MAX_SIZE		(16 << 10)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
+
+#define CONFIG_SPL_STACK		(0x40000000 + ((192 - 16) << 10))
+#define CONFIG_SPL_BOOTROM_SAVE		(CONFIG_SPL_STACK + 4)
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+
+/* SPL related SPI defines */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS		0
+#define CONFIG_SPL_SPI_CS		0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x1a000
+#define CONFIG_SYS_U_BOOT_OFFS		CONFIG_SYS_SPI_U_BOOT_OFFS
+
+/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
+#define CONFIG_DDR_FIXED_SIZE		(2 << 20)	/* 2GiB */
+
+#endif /* _CONFIG_THEADORABLE_H */
-- 
2.6.5



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