[U-Boot] [PATCH v7 2/7] mips: ath79: add support for AR933x SOCs

[Wills Wang]

On Sunday, January 17, 2016 03:31 AM, Marek Vasut wrote:
> On Saturday, January 16, 2016 at 07:13:48 PM, Wills Wang wrote:
>> This patch enable work for ar933x SOC.
> And it adds DDR code and clock code ... which is missing from the commit
> message.
These code was split in v5, the commit message before v5 was placed
in patch 1/7.
>> Signed-off-by: Wills Wang <wills.wang at live.com>
>> ---
> [...]
>
>> +void ddr_init(void)
>> +{
>> +	void __iomem *regs;
>> +	u32 val;
>> +
>> +	regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
>> +			   MAP_NOCACHE);
>> +
>> +	writel(DDR_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
>> +	writel(DDR_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
>> +
>> +	val = get_bootstrap();
>> +	if (val & AR933X_BOOTSTRAP_DDR2) {
>> +		/* AHB maximum timeout */
>> +		writel(0xfffff, regs + AR933X_DDR_REG_TIMEOUT_MAX);
>> +
>> +		/* Enable DDR2 */
>> +		writel(DDR2_CONF_VAL, regs + AR933X_DDR_REG_DDR2_CONFIG);
>> +
>> +		/* Precharge All */
>> +		writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
>> +
>> +		/* Disable High Temperature Self-Refresh, Full Array */
>> +		writel(0x00, regs + AR933X_DDR_REG_EMR2);
>> +		/* Extended Mode Register 2 Set (EMR2S) */
>> +		writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL);
>> +
>> +		writel(0x00, regs + AR933X_DDR_REG_EMR3);
>> +		/* Extended Mode Register 3 Set (EMR3S) */
>> +		writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL);
>> +
>> +		/* Enable DLL,  Full strength, ODT Disabled */
>> +		writel(0x00, regs + AR71XX_DDR_REG_EMR);
>> +		/* Extended Mode Register Set (EMRS) */
>> +		writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
>> +
>> +		/* Reset DLL */
>> +		writel(DDR2_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
>> +		/* Mode Register Set (MRS) */
>> +		writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
> Make sure that there is at least a newline before comment, to improve the
> readability of the code.
>
Ok.
>> +		/* Precharge All */
>> +		writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
>> +
>> +		/* Auto Refresh */
>> +		writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
>> +		writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
>> +
>> +		/* Write recovery (WR) 6 clock, CAS Latency 3,
>> +		 * Burst Length 8 */
> Fix the multiline comments please.
Ok.
>> +		writel(DDR2_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
>> +		/* Mode Register Set (MRS) */
>> +		writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
>> +
>> +		/* Enable OCD defaults, Enable DLL,
>> +		 * Reduced Drive Strength */
>> +		writel(DDR2_EXT_MODE_OCD_VAL, regs + AR71XX_DDR_REG_EMR);
>> +		/* Extended Mode Register Set (EMRS) */
>> +		writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
> [...]
>
>> +void ddr_tap_tuning(void)
>> +{
>> +	void __iomem *regs;
>> +	u32 *addr_k0, *addr_k1, *addr;
>> +	u32 val, tap, upper, lower;
>> +	int i, j, dir, err, done;
>> +
>> +	regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
>> +			   MAP_NOCACHE);
> Explanation of this code would be great. To an external reviewer, this
> is entirely inobvious.
>
Ok.
>> +	addr = (void *)CKSEG0ADDR(0x2000);
>> +	for (i = 0; i < 256; i++) {
>> +		val = 0;
>> +		for (j = 0; j < 8; j++) {
>> +			if (i & (1 << j)) {
>> +				if (j % 2)
>> +					val |= 0xffff0000;
>> +				else
>> +					val |= 0x0000ffff;
>> +			}
>> +
>> +			if (j % 2) {
>> +				*addr++ = val;
>> +				val = 0;
>> +			}
>> +		}
>> +	}
>> +
>> +	err = 0;
>> +	done = 0;
>> +	dir = 1;
>> +	tap = readl(regs + AR71XX_DDR_REG_TAP_CTRL0);
>> +	val = tap;
>> +	while (!done) {
>> +		err = 0;
>> +		writel(val, regs + AR71XX_DDR_REG_TAP_CTRL0);
>> +		writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1);
>> +		for (i = 0; i < 2; i++) {
>> +			addr_k1 = (void *)CKSEG1ADDR(0x2000);
>> +			addr_k0 = (void *)CKSEG0ADDR(0x2000);
>> +			addr = (void *)CKSEG0ADDR(0x3000);
>> +
>> +			while (addr_k0 < addr) {
>> +				if (*addr_k1++ != *addr_k0++) {
>> +					err = 1;
>> +					break;
>> +				}
>> +			}
>> +
>> +			if (err)
>> +				break;
>> +		}
>> +
>> +		if (err) {
>> +			if (dir) {
>> +				dir = 0;
>> +				val--;
>> +				upper = val;
>> +				val = tap;
>> +			} else {
>> +				val++;
>> +				lower = val;
>> +				done = 1;
>> +			}
>> +		} else {
>> +			if (dir) {
>> +				if (val < 0x20) {
>> +					val++;
>> +				} else {
>> +					dir = 0;
>> +					upper = val;
>> +					val = tap;
>> +				}
>> +			} else {
>> +				if (!val) {
>> +					lower = val;
>> +					done = 1;
>> +				} else {
>> +					val--;
>> +				}
>> +			}
>> +		}
>> +	}
>> +	val = (upper + lower) / 2;
>> +	writel(val, regs + AR71XX_DDR_REG_TAP_CTRL0);
>> +	val++;
>> +	writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1);
>> +}
> [...]

-- 
Best Regards
Wills