[U-Boot] [PATCH 2/2] net: phy: micrel: fix divisor value for KSZ9031 phy skew

[Marek Vasut]

On Wednesday, January 27, 2016 at 11:53:29 PM, Joe Hershberger wrote:
> Hi Marek,
> 
> On Wed, Jan 27, 2016 at 4:07 PM, Marek Vasut <marex at denx.de> wrote:
> > On Wednesday, January 27, 2016 at 10:46:00 PM,
> > dinguyen at opensource.altera.com
> > 
> > wrote:
> >> From: Dinh Nguyen <dinguyen at opensource.altera.com>
> >> 
> >> The picoseconds to register value divisor(ps_to_regval) should be 60 and
> >> not 200. Linux has KSZ9031_PS_TO_REG defined to be 60 as well. 60 is the
> >> correct divisor because the 4-bit skew values are defined from
> >> 0x0000(-420ps) to 0xffff(480ps), increments of 60.
> >> 
> >> For example, a DTS skew value of 420, represents 0ps delay, which should
> >> be 0x7. With the previous divisor of 200, it would result in 0x2, which
> >> represents a -300ps delay.
> >> 
> >> With this patch, ethernet on the SoCFPGA DE0 Atlas is now able to work
> >> with 1Gb ethernet.
> >> 
> >> References:
> >> http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf -> page 26
> >> 
> >> Signed-off-by: Dinh Nguyen <dinguyen at opensource.altera.com>
> > 
> > This is fine, thanks for spotting it.
> > 
> > Acked-by: Marek Vasut <marex at denx.de>
> > 
> > Joe, will you pick these two and push for 2016.03 or shall I pick them ?
> 
> I'll get them.

Roger, thanks!

Best regards,
Marek Vasut