[U-Boot] [PATCH 2/2] net: phy: micrel: fix divisor value for KSZ9031 phy skew

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<dinguyen at opensource.altera.com> writes:

> From: Dinh Nguyen <dinguyen at opensource.altera.com>
>
> The picoseconds to register value divisor(ps_to_regval) should be 60 and not
> 200. Linux has KSZ9031_PS_TO_REG defined to be 60 as well. 60 is the correct
> divisor because the 4-bit skew values are defined from 0x0000(-420ps) to
> 0xffff(480ps), increments of 60.
>
> For example, a DTS skew value of 420, represents 0ps delay, which should be 0x7.
> With the previous divisor of 200, it would result in 0x2, which represents a
> -300ps delay.
>
> With this patch, ethernet on the SoCFPGA DE0 Atlas is now able to work with
> 1Gb ethernet.

Is this expected to make any difference on the Altera socdk?  Both with
and without the patch, it takes a very long time (sometimes minutes) to
negotiate a link, but once it does it works fine.

> References:
> http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf -> page 26
>
> Signed-off-by: Dinh Nguyen <dinguyen at opensource.altera.com>
> ---
>  drivers/net/phy/micrel.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
> index 19b6bc7..2530a5b 100644
> --- a/drivers/net/phy/micrel.c
> +++ b/drivers/net/phy/micrel.c
> @@ -211,7 +211,7 @@ static int ksz90x1_of_config_group(struct phy_device *phydev,
>  {
>  	struct udevice *dev = phydev->dev;
>  	struct phy_driver *drv = phydev->drv;
> -	const int ps_to_regval = 200;
> +	const int ps_to_regval = 60;
>  	int val[4];
>  	int i, changed = 0, offset, max;
>  	u16 regval = 0;
> -- 
> 2.6.2

-- 
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