[U-Boot] [PATCH v2 11/15] crypto/fsl: Make CAAM transactions cacheable
Saksham Jain
saksham.jain at nxp.com
Thu Jan 28 14:20:12 CET 2016
To solve CAAM coherency issue on ls2080a and ls2085a.
When Caches are enabled and CAAM's DMA's AXI transcations are not
made cacheable, Core reads/write data from/to Caches and CAAM does from
Main Memory. This forces data flushes to synchronize various data structures
But even if any data in proximity of these structures is read by core,
these structures again are fetched in caches.
To avoid this problem, either all the data that CAAM accesses can be made
cache line aligned or CAAM transcations can be made cacheable.
So, this commit makes CAAM transcations as Write Back with Write and Read
Allocate.
Signed-off-by: Aneesh Bansal <aneesh.bansal at nxp.com>
Signed-off-by: Saksham Jain <saksham.jain at nxp.com>
---
Changes for v2:
- No changes
drivers/crypto/fsl/jr.c | 13 +++++++++++++
drivers/crypto/fsl/jr.h | 3 +++
2 files changed, 16 insertions(+)
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index b8c0c0a..01d9967 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -539,7 +539,20 @@ int sec_init(void)
uint32_t liodn_s;
#endif
+ /*
+ * Modifying CAAM Read/Write Attributes
+ * For LS2080A and LS2085A
+ * For AXI Write - Cacheable, Write Back, Write allocate
+ * For AXI Read - Cacheable, Read allocate
+ * Only For LS2080a and LS2085a, to solve CAAM coherency issues
+ */
+#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+ mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0xb << MCFGR_AWCACHE_SHIFT);
+ mcr = (mcr & ~MCFGR_ARCACHE_MASK) | (0x6 << MCFGR_ARCACHE_SHIFT);
+#else
mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT);
+#endif
+
#ifdef CONFIG_PHYS_64BIT
mcr |= (1 << MCFGR_PS_SHIFT);
#endif
diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h
index 5899696..1f2e324 100644
--- a/drivers/crypto/fsl/jr.h
+++ b/drivers/crypto/fsl/jr.h
@@ -23,6 +23,9 @@
#define MCFGR_PS_SHIFT 16
#define MCFGR_AWCACHE_SHIFT 8
#define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT)
+#define MCFGR_ARCACHE_SHIFT 12
+#define MCFGR_ARCACHE_MASK (0xf << MCFGR_ARCACHE_SHIFT)
+
#define JR_INTMASK 0x00000001
#define JRCR_RESET 0x01
#define JRINT_ERR_HALT_INPROGRESS 0x4
--
1.8.1.4
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