[U-Boot] [PATCH v1 2/2] powerpc: p2020ds: Update DDR speed tables

[York Sun]

As old DIMMs are EOL, new DIMMs need some adjustment to the
speed table. It is necessary to separate UDIMM and RDIMM for
DDR3. Verified on iDIMM M3CN-2GSF3C09-G.

Signed-off-by: York Sun <york.sun at nxp.com>

---

Changes in v1:
Initial patch to adjust DDR speed tables.

 board/freescale/p2020ds/ddr.c |   27 +++++++++++++++++++++++++--
 1 file changed, 25 insertions(+), 2 deletions(-)

diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c
index 22aff48..f7e58ef 100644
--- a/board/freescale/p2020ds/ddr.c
+++ b/board/freescale/p2020ds/ddr.c
@@ -31,7 +31,27 @@ struct board_specific_parameters {
  *  clk adjust = 0-8
  *  cpo 2-0x1E (30)
  */
-static const struct board_specific_parameters dimm0[] = {
+static const struct board_specific_parameters udimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi|  clk| cpo|wrdata|2T
+	 * ranks| mhz|adjst|    | delay|
+	 */
+#ifdef CONFIG_SYS_FSL_DDR2
+	{2,  549,    4,   0x1f,    2,  0},
+	{2,  680,    4,   0x1f,    3,  0},
+	{2,  850,    4,   0x1f,    4,  0},
+	{1,  549,    4,   0x1f,    2,  0},
+	{1,  680,    4,   0x1f,    3,  0},
+	{1,  850,    4,   0x1f,    4,  0},
+#else
+	{2,  850,    4,   0x1f,    4,  0},
+	{1,  850,    4,   0x1f,    4,  0},
+#endif
+	{}
+};
+
+static const struct board_specific_parameters rdimm0[] = {
 	/*
 	 * memory controller 0
 	 *   num|  hi|  clk| cpo|wrdata|2T
@@ -77,7 +97,10 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 		popts->cs_local_opts[i].odt_wr_cfg = 1;
 	}
 
-	pbsp = dimm0;
+	if (popts->registered_dimm_en)
+		pbsp = rdimm0;
+	else
+		pbsp = udimm0;
 
 	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
 	 * freqency and n_banks specified in board_specific_parameters table.
-- 
1.7.9.5