[U-Boot] [PATCH v2] ARM: uniphier: insert dsb barrier to ensure visibility of store

[Masahiro Yamada]

2016-06-08 18:02 GMT+09:00 Masahiro Yamada <yamada.masahiro at socionext.com>:
> I noticed secondary CPUs sometimes fail to wake up, and the root
> cause is that the sev instruction wakes up slave CPUs before the
> preceding the register write is observed by them.
>
> The read-back of the accessed register does not guarantee the order.
> In order to ensure the order between the register write and the sev
> instruction, a dsb instruction should be executed prior to the sev.
>
> Signed-off-by: Masahiro Yamada <yamada.masahiro at socionext.com>


Applied to u-boot-uniphier/master.


-- 
Best Regards
Masahiro Yamada