[U-Boot] [PATCH 1/2] sunxi: Downclock AHB1 to 100MHz on Allwinner A64

[Hans de Goede]

Hi,

On 31-05-16 00:55, Siarhei Siamashka wrote:
> On Tue, 31 May 2016 01:48:05 +0300
> Siarhei Siamashka <siarhei.siamashka at gmail.com> wrote:
>
>> Currently the AHB1 clock speed is configured as 200MHz by
>> the SPL, but this causes a subtle and hard to reproduce data
>> corruption in SRAM C (for example, this can't be easily
>> detected with a trivial memset/memcmp test).
>>
>> For what it's worth, the Allwinner's BSP configures AHB1
>> as 200MHz, as can be verified by running the devmem2 tool
>> in the system running the Allwinner's kernel 3.10.x:
>>
>>    0x1C20028: PLL_PERIPH0_CTRL_REG = 0x90041811
>>    0x1C20054: AHB1_APB1_CFG_REG    = 0x3180
>>    0x1C20058: APB2_CFG_REG         = 0x1000000
>>    0x1C2005C: AHB2_CFG_REG         = 0x1
>>
>> However the FEL mode uses more conservative settings (100MHz
>> for AHB1):
>>
>>    0x1C20028: PLL_PERIPH0_CTRL_REG = 0x90041811
>>    0x1C20054: AHB1_APB1_CFG_REG    = 0x3180
>
> Oops, a copy-paste issue when editing the commit message, this
> should be 0x3190

Thanks I've added both patches to u-boot-sunxi, with the commit
msg fixed-up. I'll send out a pull-req to get these into v2016.07
soon after this mail.

Regards,

Hans


>
>>    0x1C20058: APB2_CFG_REG         = 0x1000000
>>    0x1C2005C: AHB2_CFG_REG         = 0x0
>>
>> It is yet to be confirmed whether faster AHB1/AHB2 clock settings
>> can be used safely if we initialize the AXP803 PMIC instead of
>> using reset defaults. But in order to resolve the data corruption
>> problem right now, it's best to downclock AHB1 to a safe level.
>>
>> Note that this issue only affects the SPL, which is not fully
>> supported on Allwinner A64 yet and it should not affect the boot0
>> usage (unless somebody can confirm SRAM C corruption with the
>> boot0 too).
>>
>> Signed-off-by: Siarhei Siamashka <siarhei.siamashka at gmail.com>
>> ---
>>  arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 5 +++++
>>  1 file changed, 5 insertions(+)
>>
>> diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
>> index f2990db..c2e72f5 100644
>> --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
>> +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
>> @@ -222,7 +222,12 @@ struct sunxi_ccm_reg {
>>  #define CCM_PLL11_CTRL_UPD		(0x1 << 30)
>>  #define CCM_PLL11_CTRL_EN		(0x1 << 31)
>>
>> +#if defined(CONFIG_MACH_SUN50I)
>> +/* AHB1=100MHz failsafe setup from the FEL mode, usable with PMIC defaults */
>> +#define AHB1_ABP1_DIV_DEFAULT		0x00003190 /* AHB1=PLL6/6,APB1=AHB1/2 */
>> +#else
>>  #define AHB1_ABP1_DIV_DEFAULT		0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */
>> +#endif
>>
>>  #define AXI_GATE_OFFSET_DRAM		0
>