[U-Boot] [PATCH V2 2/3] fsl_esdhc: Update clock enable bits for USDHC

[Fabio Estevam]

On Tue, Jun 14, 2016 at 11:53 PM, Peng Fan <van.freenix at gmail.com> wrote:
> From: Ye Li <ye.li at nxp.com>
>
> The USDHC move the 4 clock bits CARD_CLK_SOFT_EN, IPG_PERCLK_SOFT_EN,
> HCLK_SOFT_EN, and IPG_CLK_SOFT_EN from sysctl register to vendorspec
> register. The driver uses RSTA to replace the clock gate off
> operation. But this is not a good solution. This is because:
> 1. when using RSTA, we should wait this bit to clear by itself. This is not
>    implemeneted in the code.
> 2. After RSTA is set, it is recommended that the Host Driver reset the
>    external card and reinitialize it.
>
> So in this patch, we change to use the vendorspec registers for these bits
> operation.
>
> Signed-off-by: Ye Li <ye.li at nxp.com>
> Signed-off-by: Peng Fan <van.freenix at gmail.com>
> Cc: York Sun <york.sun at nxp.com>
> Cc: Stefano Babic <sbabic at denx.de>
> Cc: Pantelis Antoniou <panto at antoniou-consulting.com>
> Cc: Fabio Estevam <fabio.estevam at nxp.com>

Tested-by: Fabio Estevam <fabio.estevam at nxp.com>