[U-Boot] socfpga 2016.05, CV socdk Rev E1, SPL and u-boot fail when booting from QSPI
Christian Didriksson
christian at didritec.com
Thu Jun 16 12:13:50 CEST 2016
Hi!
> On 06/15/2016 12:06 PM, Christian Didriksson wrote:
> > Trying again.
>
> Hi!
>
> > I have reverted back to a vanilla u-boot-2016.05, added the
> > not-enter-quad-mode patch
>
> What's this patch ? Can you share it ?
>
These are the changes I have made to 2016.05:
diff --git a/board/altera/cyclone5-socdk/qts/sdram_config.h b/board/altera/cyclone5-socdk/qts/sdram_config.h
index 37c1476..bd61a7a 100644
--- a/board/altera/cyclone5-socdk/qts/sdram_config.h
+++ b/board/altera/cyclone5-socdk/qts/sdram_config.h
@@ -14,8 +14,8 @@
#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 5451725..de3abca 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -1104,20 +1104,24 @@ int spi_flash_scan(struct spi_flash *flash)
/* Now erase size becomes valid sector size */
flash->sector_size = flash->erase_size;
+#ifndef CONFIG_SPL_BUILD
/* Look for the fastest read cmd */
cmd = fls(params->e_rd_cmd & spi->mode_rx);
if (cmd) {
cmd = spi_read_cmds_array[cmd - 1];
flash->read_cmd = cmd;
} else {
+#endif
/* Go for default supported read cmd */
flash->read_cmd = CMD_READ_ARRAY_FAST;
+#ifndef CONFIG_SPL_BUILD
}
/* Not require to look for fastest only two write cmds yet */
if (params->flags & WR_QPP && spi->mode & SPI_TX_QUAD)
flash->write_cmd = CMD_QUAD_PAGE_PROGRAM;
else
+#endif
/* Go for default supported write cmd */
flash->write_cmd = CMD_PAGE_PROGRAM;
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 4fdc09a..ac83ee4 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -284,22 +284,28 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
*
* device nor0 <ff705000.spi.0>, # parts = 6
* #: name size offset mask_flags
- * 0: u-boot 0x00100000 0x00000000 0
- * 1: env1 0x00040000 0x00100000 0
- * 2: env2 0x00040000 0x00140000 0
- * 3: UBI 0x03e80000 0x00180000 0
- * 4: boot 0x00e80000 0x00180000 0
- * 5: rootfs 0x01000000 0x01000000 0
+ * 0: spl 0x00040000 0x00000000 0
+ * 1: env1 0x00010000 0x00040000 0
+ * 2: dtb 0x00010000 0x00050000 0
+ * 3: u-boot 0x00080000 0x00060000 0
+ * 4: lba 0x00800000 0x000E0000 0
+ * 5: lbafs 0x01000000 0x008E0000 0
+ * 6: fpga 0x00800000 0x018E0000 0
+ * 7: script 0x00020000 0x020E0000 0
+ * 8: UBI 0x01F00000 0x02100000 0
*
*/
#if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT)
#define MTDPARTS_DEFAULT "mtdparts=ff705000.spi.0:"\
- "1m(u-boot)," \
- "256k(env1)," \
- "256k(env2)," \
- "14848k(boot)," \
- "16m(rootfs)," \
- "- at 1536k(UBI)\0"
+ "256k(spl)," \
+ "64k(env1)," \
+ "64k(dtb)," \
+ "512k(u-boot)," \
+ "8m(lba)," \
+ "16m(lbafs)," \
+ "8m(fpga)," \
+ "128k(script)," \
+ "-(UBI)\0"
#endif
/* UBI and UBIFS support */
@@ -360,7 +366,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
#ifdef CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x60000
#endif
/* SPL NAND boot support */
diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h
index a2da7d4..399f42c 100644
--- a/include/configs/socfpga_cyclone5_socdk.h
+++ b/include/configs/socfpga_cyclone5_socdk.h
@@ -24,7 +24,7 @@
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_BOOTCOMMAND "run ramboot"
#else
-#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
+#define CONFIG_BOOTCOMMAND "run qspi-boot-nga"
#endif
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
@@ -35,7 +35,18 @@
#define CONFIG_PHY_MICREL_KSZ9021
#endif
-#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SPL_SPI_SUPPORT
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET 0x00040000
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#define CONFIG_ENV_SIZE (64 * 1024)
+
+#define CONFIG_SF_DEFAULT_SPEED 50000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
+#define CONFIG_SF_DEFAULT_BUS 0
+#define CONFIG_SF_DEFAULT_CS 0
+
/* Extra Environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
@@ -58,6 +69,11 @@
"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
" ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
"bootz ${loadaddr} - ${fdt_addr}\0" \
+ "qspiloadcs=0\0" \
+ "qspiscraddr=0x020e0000\0" \
+ "qspi-boot-nga=sf probe ${qspiloadcs};" \
+ "sf read 0x100000 ${qspiscraddr} 0x10000;" \
+ "source 0x100000\0" \
"ubiload=ubi part UBI && ubifsmount ubi0 && " \
"ubifsload ${loadaddr} /boot/${bootimage} && " \
"ubifsload ${fdt_addr} /boot/${fdtimage}\0"
Some comments:
We want to run ECC, but I don't think the SPL supports scrubbing etc. yet so I undefined those qts-parameters. Am I right regarding ECC for SDRAM?
I couldn't get the SPL to work from the beginning and after much debugging I found that entering quad-mode for the flash is problematic in the SPL. At the same time I also found this, http://lists.denx.de/pipermail/u-boot/2016-June/256671.html, confirming my findings.
I have prepared the u-boot MTD-configuration for our setup.
I have added SPL SPI support and configured ENV-parameters and u-boot offset
I have also added the boot command we are going to use.
> > and changed the SPI address where the SPL should load the u-boot from
>
> Can you share this change ?
>
See above
> > and it does not work. My question:
> >
> > Has anyone else tested SPL/u-boot on an Altera CV socdk Rev E1 board
> recently (like 2016.05)? U-boot hangs after printing memory size. Same
> result using different compilers.
>
> The rev E1 is the latest SoCDK, I only have rev. C1 . I remember Dinh
> (CCed) did send a patch for the rev. E board , so I assume he did test it, but
> those were only pinmux changes and it should be part of the
> v2016.05:
>
> commit 4baca92001bff3c32a05001a7dc58996623e3ef8
> Author: Dinh Nguyen <dinguyen at kernel.org>
> Date: Tue May 10 15:13:59 2016 -0500
>
> arm: socfpga: Update iomux and pll for c5 socdk RevE
>
> Another thing which comes to mind is the change in size of SPL, that might be
> worth looking at. Can you check the size of the SPL, u-boot-spl-dtb.bin ?
>
54534 bytes
> I just tested the rev C socdk with 2016.05 and it boots for me. I will send you
> the binary I used off-list.
>
Does this SPL (loaded from QSPI by bootrom?) load u-boot from QSPI?
> > Best regards,
> >
> > Christian
> >
> > -----Ursprungligt meddelande-----
> > Från: U-Boot [mailto:u-boot-bounces at lists.denx.de] För Christian
> > Didriksson
> > Skickat: den 9 juni 2016 20:15
> > Till: u-boot at lists.denx.de
> > Ämne: [U-Boot] socfpga 2016.05, CV socdk Rev E1, SPL and u-boot fail
> > when booting from QSPI
> >
> > Hi All,
> >
> > I have been struggling for quite some time now to get SPL and u-boot to
> run from QSPI-flash. Yesterday I was able to identify a workaround to get the
> SPL going by disabling quad mode for the flash (seems identified by
> http://lists.denx.de/pipermail/u-boot/2016-June/256671.html). However u-
> boot always hangs after printing memory size. I have tried to search the
> archive and have seen posts about hanging here, but nothing I can relate to
> my setup. I have tested to use Altera's SPL (2013.01.01) and u-boot-2016.5
> and this combo seems to work.
> >
> > I also notice that the frequency (max-spi-frequency) in the dts-file is not
> picked up for some reason?
> >
> > Any help to fix the u-boot hang problem would be highly appreciated.
> >
> > Current printout (with added debug output):
> >
> > U-Boot SPL 2016.05 NGA QSPI -g133f59a-dirty (Jun 09 2016 - 17:06:20)
> > drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
> > drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
> > drivers/ddr/altera/sequencer.c: Calibration complete Trying to boot
> > from SPI
> > spl_spi_load_image: bus=0, cs=0, speed=50000000, mode=3
> > cadence_spi_ofdata_to_platdata: regbase=ff705000 ahbbase=ffa00000
> > max-frequency=500000 page-size=256
> > spi_flash_std_probe: slave=01100368, cs=0
> > SF: Read data capture delay calibrated to 7 (0 - 15)
> > cadence_spi_set_speed: speed=100000
> > cadence_spi_xfer: len=1 [bytes]
> > cadence_spi_xfer: len=5 [bytes]
> > SF: Got idcodes
> > 00000000: 20 ba 20 10 00 . ..
> > SF: Detected N25Q512
> > cadence_spi_xfer: len=1 [bytes]
> > cadence_spi_xfer: len=1 [bytes]
> > spi_flash_decode_fdt: Cannot decode address
> > cadence_spi_xfer: len=0 [bytes]
> > cadence_spi_xfer: len=0 [bytes]
> > SF: Detected N25Q512 with page size 256 Bytes, erase size 64 KiB,
> > total 64 MiB
> > SF: Read data capture delay calibrated to 7 (0 - 15)
> > cadence_spi_set_speed: speed=500000
> > cadence_spi_xfer: len=5 [bytes]
> > cadence_spi_xfer: len=64 [bytes]
> > cadence_spi_xfer: len=5 [bytes]
> > cadence_spi_xfer: len=443714 [bytes]
> >
> >
> > U-Boot 2016.05 NGA QSPI -g133f59a-dirty (Jun 09 2016 - 17:06:20 +0200)
> >
> > CPU: Altera SoCFPGA Platform
> > FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
> > BOOT: QSPI Flash (1.8V)
> > Watchdog enabled
> > I2C: ready
> > DRAM: 1 GiB
> >
> >
> > Best regards,
> >
> > Christian
> >
> >
> > _______________________________________________
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> >
>
>
> --
> Best regards,
> Marek Vasut
Best regards,
Christian
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