[U-Boot] [PATCH v5 2/5] gpio: atmel_pio4: Rework to support DM & DT
Simon Glass
sjg at chromium.org
Sun Jun 26 04:53:14 CEST 2016
Hi Wenyou,
On 19 June 2016 at 20:02, Wenyou Yang <wenyou.yang at atmel.com> wrote:
> Rework the driver to support driver model and device tree, and
> support to regard the pio4 pinctrl device as a child of
> atmel_pio4 device.
>
> Signed-off-by: Wenyou Yang <wenyou.yang at atmel.com>
> ---
>
> Changes in v5:
> - Update the clk API based on [PATCH] clk: convert API to match
> reset/mailbox fstyle (http://patchwork.ozlabs.org/patch/625342/).
> - Use clrbits_le32() to replace readl()/writel().
> - Fixed the return value, -ENODEV->-EINVAL.
> - Remove check on dev_get_parent() return.
>
> Changes in v4:
> - Remove the redundant log print.
>
> Changes in v3:
> - Add bind callback to support the pinctl device regarding as
> a child of atmel_pio4 device.
> - Add clock support.
>
> Changes in v2: None
>
> drivers/gpio/Kconfig | 2 +-
> drivers/gpio/atmel_pio4.c | 138 ++++++++++++++++++++++++++++++++++++++--------
> 2 files changed, 117 insertions(+), 23 deletions(-)
Reviewed-by: Simon Glass <sjg at chromium.org>
Minor comment below.
>
> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> index 73b862d..3332dab 100644
> --- a/drivers/gpio/Kconfig
> +++ b/drivers/gpio/Kconfig
> @@ -30,7 +30,7 @@ config DWAPB_GPIO
>
> config ATMEL_PIO4
> bool "ATMEL PIO4 driver"
> - depends on DM
> + depends on DM_GPIO
> default n
> help
> Say yes here to support the Atmel PIO4 driver.
> diff --git a/drivers/gpio/atmel_pio4.c b/drivers/gpio/atmel_pio4.c
> index 84e8cc5..d1a59ba 100644
> --- a/drivers/gpio/atmel_pio4.c
> +++ b/drivers/gpio/atmel_pio4.c
> @@ -7,11 +7,17 @@
> * SPDX-License-Identifier: GPL-2.0+
> */
> #include <common.h>
> +#include <clk_client.h>
> #include <dm.h>
> +#include <fdtdec.h>
> +#include <dm/root.h>
> #include <asm/arch/hardware.h>
> +#include <asm/gpio.h>
> #include <mach/gpio.h>
> #include <mach/atmel_pio4.h>
>
> +DECLARE_GLOBAL_DATA_PTR;
> +
> static struct atmel_pio4_port *atmel_pio4_port_base(u32 port)
> {
> struct atmel_pio4_port *base = NULL;
> @@ -165,15 +171,37 @@ int atmel_pio4_get_pio_input(u32 port, u32 pin)
> }
>
> #ifdef CONFIG_DM_GPIO
> +
> +struct atmel_pioctrl_data {
> + u32 nbanks;
> +};
> +
> +struct atmel_pio4_platdata {
> + struct atmel_pio4_port *reg_base;
> +};
> +
> +static struct atmel_pio4_port *atmel_pio4_bank_base(struct udevice *dev,
> + u32 bank)
> +{
> + struct atmel_pio4_platdata *plat = dev_get_platdata(dev);
> + struct atmel_pio4_port *port_base =
> + (struct atmel_pio4_port *)((u32)plat->reg_base +
> + ATMEL_PIO_BANK_OFFSET * bank);
> +
> + return port_base;
> +}
> +
> static int atmel_pio4_direction_input(struct udevice *dev, unsigned offset)
> {
> - struct at91_port_platdata *plat = dev_get_platdata(dev);
> - struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr;
> - u32 mask = 0x01 << offset;
> - u32 reg = ATMEL_PIO_CFGR_FUNC_GPIO;
> + u32 bank = ATMEL_PIO_BANK(offset);
> + u32 line = ATMEL_PIO_LINE(offset);
> + struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
> + u32 mask = BIT(line);
>
> writel(mask, &port_base->mskr);
> - writel(reg, &port_base->cfgr);
> +
> + clrbits_le32(&port_base->cfgr,
> + ATMEL_PIO_CFGR_FUNC_MASK | ATMEL_PIO_DIR_MASK);
>
> return 0;
> }
> @@ -181,13 +209,15 @@ static int atmel_pio4_direction_input(struct udevice *dev, unsigned offset)
> static int atmel_pio4_direction_output(struct udevice *dev,
> unsigned offset, int value)
> {
> - struct at91_port_platdata *plat = dev_get_platdata(dev);
> - struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr;
> - u32 mask = 0x01 << offset;
> - u32 reg = ATMEL_PIO_CFGR_FUNC_GPIO | ATMEL_PIO_DIR_MASK;
> + u32 bank = ATMEL_PIO_BANK(offset);
> + u32 line = ATMEL_PIO_LINE(offset);
> + struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
> + u32 mask = BIT(line);
>
> writel(mask, &port_base->mskr);
> - writel(reg, &port_base->cfgr);
> +
> + clrsetbits_le32(&port_base->cfgr,
> + ATMEL_PIO_CFGR_FUNC_MASK, ATMEL_PIO_DIR_MASK);
>
> if (value)
> writel(mask, &port_base->sodr);
> @@ -199,9 +229,10 @@ static int atmel_pio4_direction_output(struct udevice *dev,
>
> static int atmel_pio4_get_value(struct udevice *dev, unsigned offset)
> {
> - struct at91_port_platdata *plat = dev_get_platdata(dev);
> - struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr;
> - u32 mask = 0x01 << offset;
> + u32 bank = ATMEL_PIO_BANK(offset);
> + u32 line = ATMEL_PIO_LINE(offset);
> + struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
> + u32 mask = BIT(line);
>
> return (readl(&port_base->pdsr) & mask) ? 1 : 0;
> }
> @@ -209,9 +240,10 @@ static int atmel_pio4_get_value(struct udevice *dev, unsigned offset)
> static int atmel_pio4_set_value(struct udevice *dev,
> unsigned offset, int value)
> {
> - struct at91_port_platdata *plat = dev_get_platdata(dev);
> - struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr;
> - u32 mask = 0x01 << offset;
> + u32 bank = ATMEL_PIO_BANK(offset);
> + u32 line = ATMEL_PIO_LINE(offset);
> + struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
> + u32 mask = BIT(line);
>
> if (value)
> writel(mask, &port_base->sodr);
> @@ -223,9 +255,10 @@ static int atmel_pio4_set_value(struct udevice *dev,
>
> static int atmel_pio4_get_function(struct udevice *dev, unsigned offset)
> {
> - struct at91_port_platdata *plat = dev_get_platdata(dev);
> - struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr;
> - u32 mask = 0x01 << offset;
> + u32 bank = ATMEL_PIO_BANK(offset);
> + u32 line = ATMEL_PIO_LINE(offset);
> + struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
> + u32 mask = BIT(line);
>
> writel(mask, &port_base->mskr);
>
> @@ -241,21 +274,82 @@ static const struct dm_gpio_ops atmel_pio4_ops = {
> .get_function = atmel_pio4_get_function,
> };
>
> +static int atmel_pio4_bind(struct udevice *dev)
> +{
> + return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
> +}
> +
> static int atmel_pio4_probe(struct udevice *dev)
> {
> - struct at91_port_platdata *plat = dev_get_platdata(dev);
> + struct atmel_pio4_platdata *plat = dev_get_platdata(dev);
> struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
> + struct atmel_pioctrl_data *pioctrl_data;
> + struct udevice *dev_clk;
> + struct clk clk;
> + fdt_addr_t addr_base;
> + u32 nbanks;
> + int periph;
> + int ret;
> +
> + ret = clk_get_by_index(dev, 0, &clk);
> + if (ret)
> + return -EINVAL;
return ret
> +
> + periph = fdtdec_get_uint(gd->fdt_blob, clk.dev->of_offset, "reg", -1);
> + if (periph < 0)
> + return -EINVAL;
> +
> + dev_clk = dev_get_parent(clk.dev);
> + ret = clk_request(dev_clk, &clk);
> + if (ret)
> + return ret;
> +
> + clk.id = periph;
> + ret = clk_enable(&clk);
> + if (ret)
> + return ret;
> +
> + clk_free(&clk);
> +
> + addr_base = dev_get_addr(dev);
> + if (addr_base == FDT_ADDR_T_NONE)
> + return -EINVAL;
> +
> + plat->reg_base = (struct atmel_pio4_port *)addr_base;
>
> - uc_priv->bank_name = plat->bank_name;
> - uc_priv->gpio_count = ATMEL_PIO_NPINS_PER_BANK;
> + pioctrl_data = (struct atmel_pioctrl_data *)dev_get_driver_data(dev);
> + nbanks = pioctrl_data->nbanks;
> +
> + uc_priv->bank_name = fdt_get_name(gd->fdt_blob, dev->of_offset, NULL);
> + uc_priv->gpio_count = nbanks * ATMEL_PIO_NPINS_PER_BANK;
>
> return 0;
> }
>
> +/*
> + * The number of banks can be different from a SoC to another one.
> + * We can have up to 16 banks.
> + */
> +static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
> + .nbanks = 4,
> +};
> +
> +static const struct udevice_id atmel_pio4_ids[] = {
> + {
> + .compatible = "atmel,sama5d2-gpio",
> + .data = (ulong)&atmel_sama5d2_pioctrl_data,
> + },
> + {}
> +};
> +
> U_BOOT_DRIVER(gpio_atmel_pio4) = {
> .name = "gpio_atmel_pio4",
> .id = UCLASS_GPIO,
> .ops = &atmel_pio4_ops,
> .probe = atmel_pio4_probe,
> + .bind = atmel_pio4_bind,
> + .of_match = atmel_pio4_ids,
> + .platdata_auto_alloc_size = sizeof(struct atmel_pio4_platdata),
> };
> +
> #endif
> --
> 2.7.4
>
Regards,
Simon
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