[U-Boot] [PATCH 1/4] usb: phy: implement usb-otg phy control for rk3288

[Ziyuan Xu]

Apply dwc2 usb driver framework to implement phy_init and phy_off, and
enable it with CONFIG_RK3288_USB_PHY.

Signed-off-by: Ziyuan Xu <xzy.xu at rock-chips.com>
---

 drivers/usb/phy/Makefile         |  1 +
 drivers/usb/phy/rk3288_usb_phy.c | 29 +++++++++++++++++++++++++++++
 2 files changed, 30 insertions(+)
 create mode 100644 drivers/usb/phy/rk3288_usb_phy.c

diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index 93d147e..d52c42a 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -7,3 +7,4 @@
 
 obj-$(CONFIG_TWL4030_USB) += twl4030.o
 obj-$(CONFIG_OMAP_USB_PHY) += omap_usb_phy.o
+obj-$(CONFIG_RK3288_USB_PHY) += rk3288_usb_phy.o
diff --git a/drivers/usb/phy/rk3288_usb_phy.c b/drivers/usb/phy/rk3288_usb_phy.c
new file mode 100644
index 0000000..de05d4e
--- /dev/null
+++ b/drivers/usb/phy/rk3288_usb_phy.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#include "../gadget/dwc2_udc_otg_priv.h"
+
+#define GRF_UOC0_CON0		0x320
+#define SIDDQ_WRITE_ENA		BIT(29)
+#define SIDDQ_ON			BIT(13)
+#define SIDDQ_OFF			(0 << 13)
+
+void otg_phy_init(struct dwc2_udc *dev)
+{
+	/* power up usb phy analog blocks by set siddq 0 */
+	writel(SIDDQ_WRITE_ENA | SIDDQ_OFF,
+	       dev->pdata->regs_phy + GRF_UOC0_CON0);
+}
+
+void otg_phy_off(struct dwc2_udc *dev)
+{
+	/* power down usb phy analog blocks by set siddq 1 */
+	writel(SIDDQ_WRITE_ENA | SIDDQ_ON,
+	       dev->pdata->regs_phy + GRF_UOC0_CON0);
+}
-- 
1.9.1