[U-Boot] [PATCH] armv8: Enable CPUECTLR.SMPEN for data coherency

[york sun]

On 06/30/2016 02:03 AM, Gong Qianyu wrote:
> From: Mingkai Hu <mingkai.hu at nxp.com>
>
> Data coherency is enabled only when the CPUECTLR.SMPEN bit is
> set. The SMPEN bit should be set before enabling the data cache.
> If not enabled, the cache is not coherent with other cores and
> data corruption could occur.
>
> Signed-off-by: Mingkai Hu <mingkai.hu at nxp.com>
> Signed-off-by: Gong Qianyu <Qianyu.Gong at nxp.com>
>
> diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
> index 670e323..735dd67 100644
> --- a/arch/arm/cpu/armv8/start.S
> +++ b/arch/arm/cpu/armv8/start.S
> @@ -81,6 +81,11 @@ reset:
>   	msr	cpacr_el1, x0			/* Enable FP/SIMD */
>   0:
>
> +	/* Enalbe SMPEN bit */
> +	mrs     x0, S3_1_c15_c2_1               /* cpuactlr_el1 */
> +	orr     x0, x0, #0x40
> +	msr     S3_1_c15_c2_1, x0
> +
>   	/* Apply ARM core specific erratas */
>   	bl	apply_core_errata
>
>

Qianyu,

I wonder what impact this patch has. Did you find it effective on A53 
core? According to ARM documents, A57 and A72 seem don't care this bit. 
Quote

"
Note

     Any processor instruction cache and TLB maintenance operations can 
execute the request, regardless of the value of the SMPEN bit.
     This bit has no impact on data cache maintenance operations.
     In the Cortex-A57 processor, the L1 data cache and L2 cache are 
always coherent, for shared or non-shared data, regardless of the value 
of the SMPEN bit.
"

York