[U-Boot] [PATCH 01/18] at91: Add support for the AT91 slow clock controller

[Simon Glass]

This is available on AT91SAM9G45. Add the peripheral address and flag
definitions.

Signed-off-by: Simon Glass <sjg at chromium.org>
---

 arch/arm/mach-at91/include/mach/at91_sck.h    | 21 +++++++++++++++++++++
 arch/arm/mach-at91/include/mach/at91sam9g45.h |  1 +
 2 files changed, 22 insertions(+)
 create mode 100644 arch/arm/mach-at91/include/mach/at91_sck.h

diff --git a/arch/arm/mach-at91/include/mach/at91_sck.h b/arch/arm/mach-at91/include/mach/at91_sck.h
new file mode 100644
index 0000000..ce8e577
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_sck.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ * Written by Simon Glass <sjg at chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef AT91_SCK_H
+#define AT91_SCK_H
+
+/*
+ * SCKCR flags
+ */
+#define AT91SAM9G45_SCKCR_RCEN	    (1 << 0)	/* RC Oscillator Enable */
+#define AT91SAM9G45_SCKCR_OSC32EN   (1 << 1)	/* 32kHz Oscillator Enable */
+#define AT91SAM9G45_SCKCR_OSC32BYP  (1 << 2)	/* 32kHz Oscillator Bypass */
+#define AT91SAM9G45_SCKCR_OSCSEL    (1 << 3)	/* Slow Clock Selector */
+#define		AT91SAM9G45_SCKCR_OSCSEL_RC	(0 << 3)
+#define		AT91SAM9G45_SCKCR_OSCSEL_32	(1 << 3)
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index cf1c73f..5c32e24 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -109,6 +109,7 @@
 #define ATMEL_BASE_RTT		0xfffffd20
 #define ATMEL_BASE_PIT		0xfffffd30
 #define ATMEL_BASE_WDT		0xfffffd40
+#define ATMEL_BASE_SCKCR	0xfffffd50
 #define ATMEL_BASE_GPBR		0xfffffd60
 #define ATMEL_BASE_RTC		0xfffffdb0
 /* Reserved:	0xfffffdc0 - 0xffffffff */
-- 
2.8.0.rc3.226.g39d4020