[U-Boot] [PATCH 1/2] pinctrl: at91-pio4: add pinctrl driver

[Andreas Bießmann]

Dear Wenyou,

On 2016-04-07 04:15, Wenyou Yang wrote:
> AT91 PIO4 controller is a combined gpio-controller, pin-mux and
> pin-config module. The peripherals are assigned pins through per-pin
> based muxing logic. And the pin configuration are performed on
> specific registers which are shared along with the gpio controller.
> 
> Signed-off-by: Wenyou Yang <wenyou.yang at atmel.com>
> ---
> 
>  arch/arm/mach-at91/include/mach/atmel_pio4.h |  35 ++++++
>  drivers/pinctrl/Kconfig                      |   7 ++
>  drivers/pinctrl/Makefile                     |   1 +
>  drivers/pinctrl/pinctrl-at91-pio4.c          | 164 
> +++++++++++++++++++++++++++
>  4 files changed, 207 insertions(+)
>  create mode 100644 drivers/pinctrl/pinctrl-at91-pio4.c
> 
> diff --git a/arch/arm/mach-at91/include/mach/atmel_pio4.h
> b/arch/arm/mach-at91/include/mach/atmel_pio4.h
> index 8bb4b12..6760bec 100644
> --- a/arch/arm/mach-at91/include/mach/atmel_pio4.h
> +++ b/arch/arm/mach-at91/include/mach/atmel_pio4.h
> @@ -29,6 +29,41 @@ struct atmel_pio4_port {
> 
>  #endif
> 
> +/*
> + * PIO Configuration Register Fields
> + */
> +#define ATMEL_PIO_CFGR_FUNC_MASK	GENMASK(2, 0)
> +#define ATMEL_PIO_CFGR_FUNC_GPIO	(0x0 << 0)
> +#define ATMEL_PIO_CFGR_FUNC_PERIPH_A	(0x1 << 0)
> +#define ATMEL_PIO_CFGR_FUNC_PERIPH_B	(0x2 << 0)
> +#define ATMEL_PIO_CFGR_FUNC_PERIPH_C	(0x3 << 0)
> +#define ATMEL_PIO_CFGR_FUNC_PERIPH_D	(0x4 << 0)
> +#define ATMEL_PIO_CFGR_FUNC_PERIPH_E	(0x5 << 0)
> +#define ATMEL_PIO_CFGR_FUNC_PERIPH_F	(0x6 << 0)
> +#define ATMEL_PIO_CFGR_FUNC_PERIPH_G	(0x7 << 0)
> +#define ATMEL_PIO_DIR_MASK		BIT(8)
> +#define ATMEL_PIO_PUEN_MASK		BIT(9)
> +#define ATMEL_PIO_PDEN_MASK		BIT(10)
> +#define ATMEL_PIO_IFEN_MASK		BIT(12)
> +#define ATMEL_PIO_IFSCEN_MASK		BIT(13)
> +#define ATMEL_PIO_OPD_MASK		BIT(14)
> +#define ATMEL_PIO_SCHMITT_MASK		BIT(15)
> +#define ATMEL_PIO_CFGR_EVTSEL_MASK	GENMASK(26, 24)
> +#define ATMEL_PIO_CFGR_EVTSEL_FALLING	(0 << 24)
> +#define ATMEL_PIO_CFGR_EVTSEL_RISING	(1 << 24)
> +#define ATMEL_PIO_CFGR_EVTSEL_BOTH	(2 << 24)
> +#define ATMEL_PIO_CFGR_EVTSEL_LOW	(3 << 24)
> +#define ATMEL_PIO_CFGR_EVTSEL_HIGH	(4 << 24)

just realized that most of these definitions are already in the existing 
GPIO driver. Could you please put another patch before moving these 
definitions from the driver code to the header. It is ok for me to 
rephrase them when doing so.

Best regards

Andreas