[U-Boot] [PATCH v2 02/18] arm: Allow skipping of low-level init with I-cache on

[Andreas Bießmann]

Hi Simon,

On 05.05.16 15:28, Simon Glass wrote:
> At present CONFIG_SKIP_LOWLEVEL_INIT prevents U-Boot from calling
> lowlevel_init(). This means that the instruction cache is not enabled and
> the board runs very slowly.
> 
> What is really needed in many cases is to skip the call to lowlevel_init()
> but still perform CP15 init. Add an option to handle this.
> 
> Reviewed-by: Heiko Schocher <hs at denx.de>
> Tested-on: smartweb, corvus, taurus, axm
> Tested-by: Heiko Schocher <hs at denx.de>
> Reviewed-by: Joe Hershberger <joe.hershberger at ni.com>
> Signed-off-by: Simon Glass <sjg at chromium.org>
> ---
> 
> Changes in v2: None
> 
>  README                         | 5 +++++
>  arch/arm/cpu/arm1136/start.S   | 2 ++
>  arch/arm/cpu/arm920t/start.S   | 3 ++-
>  arch/arm/cpu/arm926ejs/start.S | 2 ++
>  arch/arm/cpu/arm946es/start.S  | 2 ++
>  arch/arm/cpu/armv7/start.S     | 5 ++++-
>  arch/arm/cpu/sa1100/start.S    | 2 ++
>  7 files changed, 19 insertions(+), 2 deletions(-)
> 
> diff --git a/README b/README
> index 88ff837..9ab07b5 100644
> --- a/README
> +++ b/README
> @@ -4829,6 +4829,11 @@ Low Level (hardware related) configuration options:
>  		other boot loader or by a debugger which performs
>  		these initializations itself.
>  
> +- CONFIG_SKIP_LOWLEVEL_INIT_ONLY
> +		[ARM926EJ-S only] This allows just the call to lowlevel_init()
> +		to be skipped. The normal CPU15 init (such as enabling the

CPU15 -> CP15

> +		instruction cache) is still performed.
> +
>  - CONFIG_SPL_BUILD
>  		Modifies the behaviour of start.S when compiling a loader
>  		that is executed before the actual U-Boot. E.g. when
> diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S
> index 3ebdfdd..2f8fd6a 100644
> --- a/arch/arm/cpu/arm1136/start.S
> +++ b/arch/arm/cpu/arm1136/start.S
> @@ -82,6 +82,7 @@ cpu_init_crit:
>  	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
>  	mcr	p15, 0, r0, c1, c0, 0
>  
> +#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
>  	/*
>  	 * Jump to board specific initialization... The Mask ROM will have already initialized
>  	 * basic memory.  Go here to bump up clock rate and handle wake up conditions.
> @@ -89,5 +90,6 @@ cpu_init_crit:
>  	mov	ip, lr		/* persevere link reg across call */
>  	bl	lowlevel_init	/* go setup pll,mux,memory */
>  	mov	lr, ip		/* restore link */
> +#endif
>  	mov	pc, lr		/* back to my caller */
>  #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
> diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S
> index 69cabeb..3ada6d0 100644
> --- a/arch/arm/cpu/arm920t/start.S
> +++ b/arch/arm/cpu/arm920t/start.S
> @@ -135,6 +135,7 @@ cpu_init_crit:
>  	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
>  	mcr	p15, 0, r0, c1, c0, 0
>  
> +#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
>  	/*
>  	 * before relocating, we have to setup RAM timing
>  	 * because memory timing is board-dependend, you will
> @@ -143,7 +144,7 @@ cpu_init_crit:
>  	mov	ip, lr
>  
>  	bl	lowlevel_init
> -
>  	mov	lr, ip
> +#endif
>  	mov	pc, lr
>  #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
> diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
> index f05113d..959d1ed 100644
> --- a/arch/arm/cpu/arm926ejs/start.S
> +++ b/arch/arm/cpu/arm926ejs/start.S
> @@ -101,11 +101,13 @@ flush_dcache:
>  #endif
>  	mcr	p15, 0, r0, c1, c0, 0
>  
> +#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
>  	/*
>  	 * Go setup Memory and board specific bits prior to relocation.
>  	 */
>  	mov	ip, lr		/* perserve link reg across call */
>  	bl	lowlevel_init	/* go setup pll,mux,memory */
>  	mov	lr, ip		/* restore link */
> +#endif
>  	mov	pc, lr		/* back to my caller */
>  #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
> diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S
> index 214cd8c..51053c3 100644
> --- a/arch/arm/cpu/arm946es/start.S
> +++ b/arch/arm/cpu/arm946es/start.S
> @@ -90,11 +90,13 @@ cpu_init_crit:
>  	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
>  	mcr	p15, 0, r0, c1, c0, 0
>  
> +#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
>  	/*
>  	 * Go setup Memory and board specific bits prior to relocation.
>  	 */
>  	mov	ip, lr		/* perserve link reg across call */
>  	bl	lowlevel_init	/* go setup memory */
>  	mov	lr, ip		/* restore link */
> +#endif
>  	mov	pc, lr		/* back to my caller */
>  #endif
> diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
> index b180944..691e5d3 100644
> --- a/arch/arm/cpu/armv7/start.S
> +++ b/arch/arm/cpu/armv7/start.S
> @@ -66,8 +66,10 @@ save_boot_params_ret:
>  	/* the mask ROM code should have PLL and others stable */
>  #ifndef CONFIG_SKIP_LOWLEVEL_INIT
>  	bl	cpu_init_cp15
> +#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
>  	bl	cpu_init_crit
>  #endif
> +#endif
>  
>  	bl	_main
>  
> @@ -250,7 +252,8 @@ skip_errata_621766:
>  	mov	pc, r5			@ back to my caller
>  ENDPROC(cpu_init_cp15)
>  
> -#ifndef CONFIG_SKIP_LOWLEVEL_INIT
> +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
> +	!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
>  /*************************************************************************
>   *
>   * CPU_init_critical registers
> diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S
> index 408b70d..f5318c9 100644
> --- a/arch/arm/cpu/sa1100/start.S
> +++ b/arch/arm/cpu/sa1100/start.S
> @@ -96,6 +96,7 @@ cpu_init_crit:
>  	ldr	r1, cpuspeed
>  	str	r1, [r0, #PPCR]
>  
> +#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
>  	/*
>  	 * before relocating, we have to setup RAM timing
>  	 * because memory timing is board-dependend, you will
> @@ -104,6 +105,7 @@ cpu_init_crit:
>  	mov	ip,	lr
>  	bl	lowlevel_init
>  	mov	lr,	ip
> +#endif
>  
>  	/*
>  	 * disable MMU stuff and enable I-cache
> 

Reviewed-by: Andreas Bießmann <andreas at biessmann.org>