[U-Boot] [PATCH v2] driver/ddr/fsl: Add workaround for erratum A-010165

[Shengzhou Liu]

During DDR-2133 operation, the transmit data eye margins determined
during the memory controller initialization may be sub-optimal, set
DEBUG_29[12] and DEBUG_29[13:16] = 4'b0100 before MEM_EN is set.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu at nxp.com>
---
v2: rebase

 arch/arm/include/asm/arch-fsl-layerscape/config.h |  1 +
 drivers/ddr/fsl/fsl_ddr_gen4.c                    | 10 +++++++++-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 10d17b2..5b0b4ad 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -136,6 +136,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A009663
 #define CONFIG_SYS_FSL_ERRATUM_A009803
 #define CONFIG_SYS_FSL_ERRATUM_A009942
+#define CONFIG_SYS_FSL_ERRATUM_A010165
 
 /* ARM A57 CORE ERRATA */
 #define CONFIG_ARM_ERRATA_826974
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index 608810d..4a647b0 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -56,7 +56,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	u32 vref_seq2[3] = {0xc0, 0xf0, 0x70};	/* for range 2 */
 	u32 *vref_seq = vref_seq1;
 #endif
-#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
+#if defined(CONFIG_SYS_FSL_ERRATUM_A009942) | \
+	defined(CONFIG_SYS_FSL_ERRATUM_A010165)
 	ulong ddr_freq;
 	u32 tmp;
 #endif
@@ -262,6 +263,13 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 		ddr_out32(&ddr->debug[28], tmp | 0x0060007b);
 #endif
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010165
+	ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
+	if ((ddr_freq > 1900) && (ddr_freq < 2300)) {
+		tmp = ddr_in32(&ddr->debug[28]);
+		ddr_out32(&ddr->debug[28], tmp | 0x000a0000);
+	}
+#endif
 	/*
 	 * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
 	 * deasserted. Clocks start when any chip select is enabled and clock
-- 
2.1.0.27.g96db324