[U-Boot] [PATCH v2 16/18] x86: baytrail: Add internal UART ASL description

[Bin Meng]

BayTrail integrates an internal ns15550 compatible UART (PNP0501).
Its IRQ is hardwired to IRQ3 in old revision chipset, but in newer
revision one IRQ4 is being used for ISA compatibility. Handle this
correctly in the ASL file.

Linux does not need this ASL, but Windows need this to correctly
discover a COM port existing in the system so that Windows can
show it in the 'Device Manager' window, and expose this COM port
to any terminal emulation application.

Signed-off-by: Bin Meng <bmeng.cn at gmail.com>
---

Changes in v2: None

 .../include/asm/arch-baytrail/acpi/irqlinks.asl    |  4 ++
 arch/x86/include/asm/arch-baytrail/acpi/lpc.asl    | 60 ++++++++++++++++++++++
 2 files changed, 64 insertions(+)

diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl b/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl
index aa72085..0affa23 100644
--- a/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl
+++ b/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl
@@ -21,6 +21,10 @@ Scope (\)
 		PRTF, 8,
 		PRTG, 8,
 		PRTH, 8,
+		Offset (0x88),
+		    , 3,
+		UI3E, 1,
+		UI4E, 1
 	}
 }
 
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
index 1dca977..385671c 100644
--- a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
+++ b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
@@ -14,6 +14,15 @@ Device (LPCB)
 {
 	Name(_ADR, 0x001f0000)
 
+	OperationRegion(LPC0, PCI_Config, 0x00, 0x100)
+	Field(LPC0, AnyAcc, NoLock, Preserve) {
+		Offset(0x08),
+		SRID, 8,
+		Offset(0x80),
+		C1EN, 1,
+		Offset(0x84)
+	}
+
 	#include "irqlinks.asl"
 
 	/* Firmware Hub */
@@ -81,6 +90,57 @@ Device (LPCB)
 		}
 	}
 
+	/* Internal UART */
+	Device (IURT)
+	{
+		Name(_HID, EISAID("PNP0501"))
+		Name(_UID, 1)
+
+		Method(_STA, 0, Serialized)
+		{
+			/*
+			 * TODO:
+			 *
+			 * Need to hide the internal UART depending on whether
+			 * internal UART is enabled or not so that external
+			 * SuperIO UART can be exposed to system.
+			 */
+			Store(1, UI3E)
+			Store(1, UI4E)
+			Store(1, C1EN)
+			Return (STA_VISIBLE)
+
+		}
+
+		Method(_DIS, 0, Serialized)
+		{
+			Store(0, UI3E)
+			Store(0, UI4E)
+			Store(0, C1EN)
+		}
+
+		Method(_CRS, 0, Serialized)
+		{
+			Name(BUF0, ResourceTemplate()
+			{
+				IO(Decode16, 0x03f8, 0x03f8, 0x01, 0x08)
+				IRQNoFlags() { 3 }
+			})
+
+			Name(BUF1, ResourceTemplate()
+			{
+				IO(Decode16, 0x03f8, 0x03f8, 0x01, 0x08)
+				IRQNoFlags() { 4 }
+			})
+
+			If (LLessEqual(SRID, 0x04)) {
+				Return (BUF0)
+			} Else {
+				Return (BUF1)
+			}
+		}
+	}
+
 	/* Real Time Clock */
 	Device (RTC)
 	{
-- 
1.8.2.1