[U-Boot] [PATCH 8/9][v2] armv8: ls1012a: Add support of ls1012aqds board

[Edward L Swarthout]

From: York Sun
> On 05/11/2016 12:30 AM, Prabhakar Kushwaha wrote:
> > QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
> >...
> > +++ b/include/configs/ls1012a_common.h
> >...
> > +#define CONFIG_SYS_CLK_FREQ          100000000
> > +#define CONFIG_DDR_CLK_FREQ          125000000
>
> Hard-coded value? Are the clocks board-specfic?

There is no separate DDR clock input,
so the DDR frequency should be derived from SYS_CLK and it can only be 4x.

> > +
> > +/* Generic Timer Definitions */
> > +#define COUNTER_FREQUENCY            25000000        /* 12MHz */
>
> Does this timer has a dedicated clock source? This should be
> CONFIG_SYS_CLK_FREQ/4, right? Isn't it also board-specific?

The SOC RM section 7.1.1.5.2 says it always SYSCLK_FREQ/4,
so doesn't this belong in arch-fsl-layerscape/config.h?

> > +++ b/include/configs/ls1012aqds.h
> > +#include "ls1012a_common.h"
>
> Shouldn't sysclk/ddrclk be put here?

Yes.

In addition, the SYS_CLK on the QDS can be controlled with a fine granularity
and the actual frequency can be obtained from the QIXIS FPGA.

Patch 5 in this series wasn't commented on, but it adds LS1012 specif hacks to the 
supposedly generic fsl_lsch2_speed function to compute freq_systembus and freq_ddrbus.

For ls1012 there is no need to look at the RCW, the freq_systembus is always 2x SYS_CLK.

Ed