[U-Boot] Altera Cyclone 5 UART Communication Issues - U-Boot 2016.03

[Nathan Barrett]

Hello All,

I'm currently running U-Boot 2016.03 on a Terasic SoC Kit without any apparent issues.

However, when I go to run the same build on our custom board, the debug port's UART0 RXD fails to receive any key presses when I'm attempting to stop autoboot.

On both boards, the debug UART0 TX and RX lines are using the same pins for.  The only difference between the boards is that our custom board is routing the UART TX and RX lines through the FPGA fabric.

I'm making sure to start up the FPGA with these few additional lines in the boot sequence:

#fatload mmc 0:${mmcloadpart} 0x2000000 soc_system.rbf; fpga load 0 0x2000000 0x23C1B4;

I can tell that the FPGA does seem to be running fine, as the UART TX is coming through (I see all the proper boot info) and an FPGA controlled heartbeat LED starts blinking.


Does anyone have any insight into what could be going on?


Thank you,

Nathan Barrett

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